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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr17v358 high performance octal pci express uart april 2012 rev. 1.0.4 general description the xr17v358 1 (v358) is a single chip 8-channel pci express (pcie) uart (universal asynchronous receiver and transmitter), optimized for higher performance and lower power. the v358 serves as a single lane pcie bridge to 8 indepedent enhanced 16550 compatible uarts. the v358 is compliant to pcie 2.0 gen 1 (2.5gt/s). in addition to the uart channels, the v358 has 16 multi-purpose i/os (mpios), a 16-bit general purpose counter/timer and a global interrupt status register to optimize interr upt servicing. each uart of the v358 has many enhanced features such as the 256- bytes tx and rx fifos, programmable fractional baud rate generator, automatic hardware or soft ware flow control, auto rs-485 half-duplex direction control, programmable tx and rx fifo trigger levels, tx and rx fifo level counters, infrared mode, and data rates up to 25mbps. the v358 is available in a 176-pin fpbga package (13 x 13 mm). n ote 1: covered by u.s. patents #5,649,122, #6,754,839, #6,865,626 and #6,947,999 applications ? next generation point-of-sale systems ? remote access servers ? storage network management ? factory automation and process control ? multi-port rs-232/rs-422/rs-485 cards features ? single 3.3v power supply ? internal buck regulator for 1.2v core ? pcie 2.0 gen 1 compliant ? x1 link, dual simplex, 2.5gbps in each direction ? expansion bus interface ? eeprom interface fo r configuration ? global interrupt status register for all eight uarts ? up to 25 mbps serial data rate ? 16 multi-purpose inputs/outputs (mpios) ? 16-bit general purpose timer/counter ? sleep mode with wake-up indicator ? eight independent uart channels controlled with 16550 compatible register set 256-byte tx and rx fifos programmable tx and rx trigger levels tx/rx fifo level counters fractional baud rate generator automatic rts/cts or dtr/dsr hardware flow control with programmable hysteresis automatic xon/xoff software flow control rs-485 half duplex direction control output with programmable turn-around delay multi-drop with auto address detection infrared (irda 1.1) data encoder/decoder ? software compatible to xr17c15x, xr17d15x, xr17v25x pci uarts f igure 1. b lock d iagram of the xr17v358 global configuration registers crystal osc/buffer pci local bus interface configuration space registers multi- purpose inputs/outputs 16-bit timer/counter uart channel 0 64- byte tx fifo 64- byte rx fifo brg ir endec tx & rx uart regs tx+ rx+ eeck eedo eecs uart channel 1 uart channel 2 uart channel 3 uart channel 4 uart channel 5 uart channel 6 uart channel 7 tmrck rx[7:0] tx[7:0] rts#[7:0] dtr#[7:0] c t s #[7 :0] d s r #[7 :0] dcd#[7:0] m p io [7 :0] ri#[7:0] eeprom interface global configuration registers global configuration registers pcie interface configuration space registers multi- purpose inputs/outputs multi-purpose inputs/outputs 16-bit timer/counter 16-bit timer/counter uart channel 0 64- byte tx fifo 64- brg ir endec tx & rx uart regs uart channel 0 256-byte tx fifo brg ir endec tx & rx uart regs eedi uart channel 1 uart channel 2 uart channel 3 uart channel 4 uart channel 5 uart channel 6 uart channel 7 tmrck r x [7:0] tx[7:0] rts#[7:0] dtr#[7:0] c t s #[7 :0] d s r #[7 :0] dcd#[7:0] m p io [7 :0] mpio[15:0] ri#[7:0] enir# eeprom interface eeprom interface 256-byte rx fifo tx- rx- clk+ clk- clkreq# perst# en485# expansion in te rfac e d[7:0] sel in t mode clk buck regulator 125 mhz clock pres
f igure 2. 176-fpbga p inout transparent top view a1 corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r nc tx5 ri4 gnd cts4# tx4 dsr2# gnd rts2# tmrck test2 gnd lx lx nc cd5# dtr5# cts5# cd4# dtr4# rx4 cd2# dtr2# rx2 enir# test1 gnd vcc33 vcc33 vcc33 mpio0 ri5# dsr5# rts5# dsr4# rts4# ri2# cts2# tx2 en485# fb gnd vcc33 enable d0 mpio2 mpio1 rx5 gnd vcc33 gnd vcc12 gnd vcc33 gnd vcc12 gnd pwrgd int d2 mpio5 mpio4 gnd test0 rx+ rx- gnd gnd tx+ tx- gnd vcc12 clkreq# perst# gnd mpio8 mpio11 mpio14 tms gnd vcc33 gnd vcc12 gnd cd7# eedo rx0 dsr0# gnd mpio9 mpio12 mpio15 trst# tx3 cts3# cd3# ri3# dsr6# tx7 cts7# ri7# tx0 cts0# dtr0# mpio10 mpio13 tck tdo rts3# dtr3# rts6# rx6 dtr6# ri6# rx7 dtr7# eeck eedi rts0# nc reset# tdi gnd rx3 dsr3# tx6 gnd cts6# cd6# rts7# gnd dsr7# eecs nc d3 d4 d6 d7 clk mode pres gnd dsr1# cd1# rx1 cts1# ri0# tx1 mpio3 vcc12 mpio6 gnd gnd clk+ rext clk- gnd gnd vcc33 vcc12 mpio7 gnd vcc33 d1 gnd d5 vcc12 sel gnd ri1# vcc33 dtr1# gnd rts1# vcc12 cd0# a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr17v358ib176-f 176-fpbga -40c to +85c active xr17v358 2 high performance octal pci express uart rev. 1.0.4
xr17v358 3 rev. 1.0.4 high performance octal pci express uart pin descriptions n ame p in # t ype d escription pcie signals clk+ clk- g4 h4 i i pcie reference clock input. tx+ tx- j1 j2 o o pcie differential tx outputs rx+ rx- g1 g2 i i pcie differential rx inputs clkreq# l1 o pcie edge connector clock request perst# l2 i pcie edge connector reset rext h3 connect a 191 ohm 1% resistor to gnd. this is used for pcie phy calibra - tion. modem or serial i/o interface tx0 n13 o uart channel 0 transmit data or infrared transmit data. rx0 m13 i uart channel 0 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted internally prior to decoding by setting fctr bit [4]. rts0# p15 o uart channel 0 request to send or ge neral purpose output (active low). cts0# n14 i uart channel 0 clear to send or ge neral purpose input (active low). dtr0# n15 o uart channel 0 data terminal ready or general purpose output (active low). dsr0# m14 i uart channel 0 data set ready or general purpose input (active low). cd0# l13 i uart channel 0 carrier detect or general purpose input (active low). ri0# l14 i uart channel 0 ring indicator or general purpose input (active low). tx1 l15 o uart channel 1 transmit data or infrared transmit data. rx1 k14 i uart channel 1 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts1# k13 o uart channel 1 request to send or ge neral purpose output (active low). cts1# k15 i uart channel 1 clear to send or ge neral purpose input (active low). dtr1# j13 o uart channel 1 data terminal ready or general purpose output (active low). dsr1# j14 i uart channel 1 data set ready or general purpose input (active low). cd1# j15 i uart channel 1 carrier detect or general purpose input (active low). ri1# h13 i uart channel 1 ring indicator or general purpose input (active low). tx2 c9 o uart channel 2 transmit data or infrared transmit data.
xr17v358 4 high performance octal pci express uart rev. 1.0.4 rx2 b9 i uart channel 2 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts2# a9 o uart channel 2 request to send or gen eral purpose output (active low). cts2# c8 i uart channel 2 clear to send or ge neral purpose input (active low). dtr2# b8 o uart channel 2 data terminal ready or general purpose output (active low). dsr2# a7 i uart channel 2 data set ready or general purpose input (active low). cd2# b7 i uart channel 2 carrier detect or general purpose input (active low). ri2# c7 i uart channel 2 ring indicator or general purpose input (active low). tx3 n5 o uart channel 3 transmit data or infrared transmit data. rx3 r5 i uart channel 3 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts3# p5 o uart channel 3 request to send or gen eral purpose output (active low). cts3# n6 i uart channel 3 clear to send or ge neral purpose input (active low). dtr3# p6 o uart channel 3 data terminal ready or general purpose output (active low). dsr3# r6 i uart channel 3 data set ready or general purpose input (active low). cd3# n7 i uart channel 3 carrier detect or general purpose input (active low). ri3# n8 i uart channel 3 ring indicator or general purpose input (active low). tx4 a6 o uart channel 4 transmit data or infrared transmit data. rx4 b6 i uart channel 4 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts4# c6 o uart channel 4 request to send or gen eral purpose output (active low). cts4# a5 i uart channel 4 clear to send or ge neral purpose input (active low). dtr4# b5 o uart channel 4 data terminal ready or general purpose output (active low). dsr4# c5 i uart channel 4 data set ready or general purpose input (active low). cd4# b4 i uart channel 4 carrier detect or general purpose input (active low). ri4# a3 i uart channel 4 ring indicator or general purpose input (active low). tx5 a2 o uart channel 5 transmit data or infrared transmit data. rx5 d3 i uart channel 5 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts5# c4 o uart channel 5 request to send or gen eral purpose output (active low). pin descriptions n ame p in #t ype d escription
xr17v358 5 rev. 1.0.4 high performance octal pci express uart cts5# b3 i uart channel 5 clear to send or ge neral purpose input (active low). dtr5# b2 o uart channel 5 data terminal ready or general purpose output (active low). dsr5# c3 i uart channel 5 data set ready or general purpose input (active low). cd5# b1 i uart channel 5 carrier detect or general purpose input (active low). ri5# c2 i uart channel 5 ring indicator or general purpose input (active low). tx6 r7 o uart channel 6 transmit data or infrared transmit data. rx6 p8 i uart channel 6 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts6# p7 o uart channel 6 request to send or ge neral purpose output (active low). cts6# r9 i uart channel 6 clear to send or ge neral purpose input (active low). dtr6# p9 o uart channel 6 data terminal ready or general purpose output (active low). dsr6# n9 i uart channel 6 data set ready or general purpose input (active low). cd6# r10 i uart channel 6 carrier detect or general purpose input (active low). ri6# p10 i uart channel 6 ring indicator or general purpose input (active low). tx7 n10 o uart channel 7 transmit data or infrared transmit data. rx7 p11 i uart channel 7 receive data or infrared receive data. normal rxd input idles at high condition. the infrared pulses can be inverted prior to decoding by setting fctr bit [4]. rts7# r11 o uart channel 7 request to send or ge neral purpose output (active low). cts7# n11 i uart channel 7 clear to send or ge neral purpose input (active low). dtr7# p12 o uart channel 7 data terminal ready or general purpose output (active low). dsr7# r13 i uart channel 7 data set ready or general purpose input (active low). cd7# m11 i uart channel 7 carrier detect or general purpose input (active low). ri7# n12 i uart channel 7 ring indicator or general purpose input (active low). expansion interface mode g15 i expansion interface mode select. connect this pin to vcc to enable master mode or when there is no slave device. connect this pin to gnd when the device is in slave mode. clk g14 i/o expansion interface clock. in master mo de, this pin is the clock output to the slave device. in slave mode, this pi n is the clock input from the master device. the expansion interface clock is 62.5mhz. the uarts on the slave device will need to use different baud rate generator divisors than the master device. the trace capacitance between t he master and slave device must be less than 25pf. pin descriptions n ame p in #t ype d escription
xr17v358 6 high performance octal pci express uart rev. 1.0.4 d7 f15 i/o expansion interface data 7 (msb). th e trace capacitance between the mas - ter and slave device must be less than 25pf. d6 f14 i/o expansion interface data 6. the trac e capacitance between the master and slave device must be less than 25pf. d5 f13 i/o expansion interface data 5. the trac e capacitance between the master and slave device must be less than 25pf. d4 e15 i/o expansion interface data 4. the trac e capacitance between the master and slave device must be less than 25pf. d3 e14 i/o expansion interface data 3. the trac e capacitance between the master and slave device must be less than 25pf. d2 d15 i/o expansion interface data 2. the trac e capacitance between the master and slave device must be less than 25pf. d1 e13 i/o expansion interface data 1. the trac e capacitance between the master and slave device must be less than 25pf. d0 c15 i/o expansion interface data 0 (lsb). the trace capacitance between the master and slave device must be less than 25pf. sel g13 i/o expansion interface read/write select. th is is the the read/write select input in the slave mode. this is the read/wri te select output in the master mode. this pin can be left unconnected if t here is no slave device. the trace capaci - tance between the master and sl ave device must be less than 25pf. int d14 i/o expansion interface interrupt. this is the expansion interface interrupt output in the slave mode. this is the expans ion interface interrupt input in the mas - ter mode. this pin can be left unconnec ted if there is no slave device. the trace capacitance between the master a nd slave device must be less than 25pf. pres h14 i slave present. in master mode, connect this pin to vcc if there is a slave device present. connect this pin to gnd to disable access to the slave device (slave device may or may not be present). in slave mode, this pin should be connected to gnd. mpio signals mpio0 c1 i/o multi-purpose input/output 0. the function of this pin is defined thru the con - figuration register mpiosel, mpio lvl, mpioinv, mpio3t and mpioint mpio1 d2 i/o multi-purpose input/output 1. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio2 d1 i/o multi-purpose input/output 2. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio3 e3 i/o multi-purpose input/output 3. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio4 e2 i/o multi-purpose input/output 4. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio5 e1 i/o multi-purpose input/output 5. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. pin descriptions n ame p in #t ype d escription
xr17v358 7 rev. 1.0.4 high performance octal pci express uart mpio6 f3 i/o multi-purpose input/output 6. the functi on of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio7 l3 i/o multi-purpose input/output 7. the functi on of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio8 m2 i/o multi-purpose input/output 8. the functi on of this pin is defined thru the con - figuration register mpiosel, mpio lvl, mpioinv, mpio3t and mpioint mpio9 n1 i/o multi-purpose input/output 9. the functi on of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio10 p1 i/o multi-purpose input/output 10. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio11 m3 i/o multi-purpose input/output 11. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio12 n2 i/o multi-purpose input/output 12. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio13 p2 i/o multi-purpose input/output 13. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio14 m4 i/o multi-purpose input/output 14. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. mpio15 n3 i/o multi-purpose input/output 15. the function of this pin is defined thru the con - figuration register mpiosel, mpiolv l, mpioinv, mpio3t and mpioint. eeprom signals eeck p13 o serial clock to eeprom. an internal clock of clk divide by 256 is used for reading the vendor and sub-vendor id du ring power up or reset. however, it can be manually clocked thru the configuration register regb. eecs r14 o chip select to a eeprom device like 93c 46. it is manually selectable thru the configuration register regb. requi res a pull-up 4.7k ohm resistor for external sensing of eeprom during power up. eedi p14 o write data to eeprom device. it is manually accessible th ru the configura - tion register regb. eedo m12 i read data from eeprom device. it is manually accessible thru the configu - ration register regb. jtag signals trst# n4 i jtag test reset. this signal is active low. tck p3 i jtag test clock tms m5 i jtag test mode select tdi r3 i jtag data input tdo p4 o jtag data output buck regulator signals enable c14 i connect to vcc to enable buck regulator. connect to gnd to disable buck regulator. pin descriptions n ame p in #t ype d escription
xr17v358 8 high performance octal pci express uart rev. 1.0.4 n ote : pin type: i=input, o=output, io= in put/output, od=output o pen drain, ot=output tristate, is=input schmitt trigger. lx lx a13 a14 o o connect these two signals togethe r to external 4.7uh inductor. fb c11 i connect this signal to other end of external 4.7uh inductor. 47uf capacitor to gnd is also required on this pin. pwrgd d13 o indicates that 1.2v core has been powered up. ancillary signals reset# r2 i system reset (active low). in normal operation, this signal should be high. tmrck a10 i 16-bit timer/counter ex ternal clock input. en485# c10 i auto rs-485 mode enable (active low). this pin is sampled during power up, following a hardware reset (rst#) or so ft reset (register reset). it can be used to start up all 8 uarts in the auto rs-485 half-duplex direction control mode. the sampled logic state is transferred to fctr bit-5 in the uart channel. enir# b10 i infrared mode enable (active low). this pin is sampled during power up, fol - lowing a hardware reset (rst#) or soft-reset (register reset). it can be used to start up all 8 uarts in the infrared mode. the sampled logic state is transferred to mcr bit-6 in the uart. test0 test1 test2 f2 b11 a11 i i i factory test modes. for norm al operation, connect to gnd. vcc33 d5, d9, e12, j12, m7 pwr 3.3v i/o power supply. vcc33a k3 pwr 3.3v analog phy power supply. a ferrite bead is recommended on this pin. vcc33p b13, c13 pwr 3.3v power supply voltage for output stage of buck regulator. vcc33b b14, b15 pwr 3.3v power supply for the anal og blocks of the buck regulator. vcc12 d7, d11, e4, g12, k4, l12, m9 pwr 1.2v core power supply. a ferrite bead is recommended on these pins. vcc12a k2 pwr 1.2v analog phy power supply. a ferrite bead is recommended on this pin. gnd a4, a8, a12, b12, c12, d4, d6, d8, d10, d12, f1, f4, f12, g3, h1, h2, h12, h15, j3, j4, k1, k12, l4, m1, m6, m8, m10, m15, r4, r8, r12 pwr power supply common, ground. nc a1, a15, r1, r15 - no internal connection. pin descriptions n ame p in #t ype d escription
xr17v358 9 rev. 1.0.4 high performance octal pci express uart functional description the xr17v358 (v358) integrates the functions of eight independent enhanced 16550 uarts, a general purpose 16-bit timer/counter, and 16 multi-purpose i/ os (mpios). each uart channel has its own 16550 uart compatible configuration register set for individual channel control, status and data transfer. the device configuration registers include a set of four consecutive interrupt source regi sters that provides interrupt status for all eight uarts, timer/counter, mpios and a sleep wake-up indicator. additionally, each uart channel has 256-byte of transmit and receive fifos, automatic rts/cts or dtr/dsr hardware flow control, automatic xon/xoff, special character flow control, programmable transmit and receive fifo trigger levels, infrared encoder/decoder (irda ver. 1.1), and a programmable frac tional baud rate generator with a prescaler of divide by 1 or 4, and a data rate up to 25 mbps with the 4x sampling rate. pci l ocal b us c onfiguration s pace r egisters a set of local bus configuration space register is provided. these register s provide the pci vendor id, device id, sub-vendor id, prod uct model number, resources an d capabilities which is collect ed by the host during the auto configuration phase th at follows immediately after a power up or system reset/reboot. after the host has sorted out all devices on the bus, it defines and downlo ad the operating conditions to the cards. one of the definitions is the base addr ess loaded into the base address register (bar) wher e the card will be operating in the pci local bus memory space. all this is described in more detail in ?section 1.1, pci local bus configuration space registers? on page 10 . eeprom i nterface an external 93c46 eeprom is used to store words of information such as pci vendor id, pci device id, class code, etc. details of this information can be found in ?section 1.2, eeprom interface? on page 14 . this information is only used with the plug-and-play auto configuration of the pci local bus. these data provide automatic hardware installation onto the pci bus. the eeprom interface consists of 4 signals, eedi, eedo, eecs, and eeck. the eeprom is not needed when auto configuration is not required in the application. however, if your design requires non- volatile memory for other purpose, it is possible to store and retrieve data on the eeprom through a special pci device configuration register. see application note dan112 for its programming details.
xr17v358 10 high performance octal pci express uart rev. 1.0.4 1.0 xr17v358 internal registers the xr17v358 uart register set is very similar to the previous generation pci uarts. this makes the v358 software compatible with the previous generation pci uarts. minimal changes are needed to the software driver of an existing exar pci uart driver so that it can be used with the v358 pcie uart. there are three different sets of registers as shown in figure 3 . the pci local bus configuration space registers is needed for plug-and-play auto-configuration. this auto-configuration feature makes installation very easy into a pci system and it is part of the pci lo cal bus specification. the second register set is the device configuration registers that are also accessible directly from the pci bus for programming general operating conditions of the device and monitoring the status of vari ous functions common to all eight channels. these functions include all 8 channel uarts? interrupt co ntrol and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and stat us, sleep mode, soft-reset, and device identification and revision. and lastly, each uart channel has its own set of internal uart configuration registers for its own operation control and status reporting. all 8 sets of channel registers are embedded inside the device configuration registers space, which pr ovides faster access. the second and third set of registers are mapped into 8k of the pci bus memory address space. the fo llowing paragraphs describe all 3 sets of registers in detail. f igure 3. t he xr17v358 r egister s ets channel 0 in t, m pio , timer, reg device configuration and uart[7:0] configuration registers are mapped on to the base address register (bar) in a 8k- byte of memory address space pci local bus interface channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 device configuration registers 8 channel interrupts, multipurpose i/os, 16-bit timer/counter, sleep, r eset, d vid , d r ev uart[7:0] configuration registers 16550 compatible and exar enhanced registers pci local bus configuration space registers for plug- and-play auto configuration vendor and sub-vendor id and product model number in external eeprom 0x0000 0x0400 0x0800 0x0c00 0x1000 0x1400 0x1800 0x1c00 0x0080 0x1fff 1.1 pci local bus configuration space registers the pci local bus configuration space registers are responsible for setting up the device?s operating environment in the pci local bus. the pre-defined operating parameters of the device is read by the pci bus plug-and-play auto-conf iguration manager in the o perating system. after the pci bus has collected all data from every device/card on the bus, it defines and dow nloads the memory mapping information to each device/ card about their individual operation memory address location and conditions. the operating memory mapped address location is downloaded into the base address regi ster (bar) register, located at an address offset of 0x10 in the configuration space. custom modification of certain registers is possible by using an external 93c46 eeprom. the eeprom contains th e device vendor and su b-vendor data, along with 6 other words of information (see ?section 1.2, eeprom interface? on page 14 ) required by the auto-configuration setup.
xr17v358 11 rev. 1.0.4 high performance octal pci express uart t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary ) 0x00 31:16 ewr device id - no slave device on expansion interface device id - xr17v358 slave device on expansion interface device id - xr17v354 slave device on expansion interface 0x0358 0x8358 0x4358 15:0 ewr vendor id (exar) specified by pcisig 0x13a8 0x04 31 30 rwc rwc parity error detected. cleared by writing a logic 1. system error detected. cleared by writing a logic 1. 0b 0b 29:28 ro unused 00b 27 ro target abort. 0b 26:25 ro devsel# timing. 00b 24 ro unemployments bus master error reporting bit 0b 23 ro fast back to back transactions are supported 0b 22 ro reserved status bit 0b 21 ro 66mhz capable 0b 20 ro capabilities list 1b 19:16 ro reserved status bits 0000b 15:11, 9,7, 5, 4, 3, 2 ro command bits (reserved) 0x0000 10 rwr this bit disables the device from asserting intx#. logic 1 = dis - able assertion of intx# and logic 0 = enables assertion of intx# 0b 8 rwr serr# driver enable. logic 1=enable driver and 0=disable driver 0b 6 rwr parity error enable. logic 1=respond to parity error and 0=ignore 0b 1 rwr command controls a device?s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0b 0 ro device?s response to i/o space accesses is disabled. (0 = disable i/o space accesses) 0b 0x08 31:8 ewr class code (default is ?simpl e 550 communication controller?) 0x070002 7:0 ro revision id (exar devi ce revision number) current rev. value 0x0c 31:24 ro bist (built-in self test) 0x00 23:16 ro header type (a single function device with one bar) 0x00 15:8 ro unimplemented latency timer (needed only for bus master) 0x00 7:0 ro unimplemented cache line size 0x00 0x10 31:14 rwr memory base address register (bar0) 0x00000 13:0 ro claims an 16k address space for the memory mapped uarts including the uarts on the expansion interface. 0x0000
xr17v358 12 high performance octal pci express uart rev. 1.0.4 0x14 31:0 rwr unimplemented base addre ss register (returns zeros) 0x00000000 0x18h 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x1c 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x20 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x24 31:0 ro unimplemented base addre ss register (returns zeros) 0x00000000 0x28 31:0 ro reserved 0x00000000 0x2c 31:16 ewr subsystem id (write from external eeprom by customer) 0x0000 15:0 ewr subsystem vendor id (write from external eeprom by cus - tomer) 0x0000 0x30 31:0 ro expansion rom base address (unimplemented) 0x00000000 0x34 31:8 ro reserved (returns zeros) 0x000000 7:0 ro capability pointer 0x50 0x38 31:0 ro reserved (returns zeros) 0x00000000 0x3c 31:24 ro unimplemented maxlat 0x00 23:16 ro unimplemented mingnt 0x00 15:8 ro interrupt pin, use inta#. 0x01 7:0 rwr interrupt line. 0xxx 0x40 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x44 31:0 ro csr 0x02106160 0x48 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x4c 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x50 31:16 ro 64-bit address capable 0x0080 15:8 ro next capability pointer 0x78 7:0 ro msi capable capability id 0x05 0x54-0x67 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x68 31:0 ro not implemented or not applicable 0x0000xxxx 0x6c-0x77 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x78 31:16 ro pme# support (pme# can be asserted from d3hot and d0) pci power management 1.2 0x4803 15:8 ro next capability pointer 0x80 7:0 ro power management capability id 0x01 0x7c 31:0 ro no soft reset when transiti oning from d3hot to d0 state 0x00000008 t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary )
xr17v358 13 rev. 1.0.4 high performance octal pci express uart 0x80 31:16 ro pci express 2.0 capable endpoint, interrupt message number 1 0x0202 15:8 ro next capability pointer 0x00 7:0 ro pci express capability id 0x10 0x84 31:16 ro not implemented or not applicable (return zeros) 0x0000 15:8 ro role-based error reporting 0x80 7:0 ro 256 bytes max payload size 0x01 0x88 31:16 rw not implemented or not applicable (return zeros) 0x0000 15:8 rw 512 bytes max read request, enable no snoop 0x28 7:0 rw 256 bytes max tlp payload size 0x10 0x8c 31:24 ro port number 0x01 23:22 ro not implemented or not applicable (return zeros) 00b 21:18 ro not implemented or not applicable (return zeros) 0000b 17:15 ro l1 exit latency < 1 us 000b 14:12 ro l0s exit latency < 64 ns 000b 11:10 ro active state power m anagement (aspm) support l0s and l1 supported 11b 9:4 ro x1 max link width 000001b 3:0 ro 2.5gt/s link speed supported 0001b 0x90 31:21 ro not implemented or not applicable (return zeros) 00000000000b 20 ro data link layer active reporting capable 1b 19 ro surprise down error reporting not supported 0b 18 ro reference clock must not be removed. 0b 17:15 ro l1 exit latency - 2 us to less than 4 us 010b 14:10 ro not implemented or not applicable (return zeros) 00000b 9:4 ro x1 negotiated link width 000001b 3:0 ro current link speed is 2.5gt/s 0001b 0x94 31:0 ro pcie capability offset 0x14 - slot capabilities register 0x00040000 0x98-0xaf 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0xb0 31:0 ro pcie capability offset 0x30 - link status2/control2 0x00010001 0xb4-0xff 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x100 31:0 ro vc resource capability register 0x00010002 t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary )
xr17v358 14 high performance octal pci express uart rev. 1.0.4 n ote : ewr=read/write from external eeprom. rwr=read /write. ro= read only. rwc=read/write-clear. 1.2 eeprom interface the v358 provides an interf ace to an electrically erasable program mable read only memo ry (eeprom). the eeprom must be a 93c46-like de vice, with its memory config ured as 16-bit words. this interface is provided in order to program the registers in the pci configuration space of the pci uart during power-up. the eeprom must be organ ized into address/data pa irs. the first word of the pair is the address and the second word is the data. table 2 below shows the format of the 16-bit address: t able 2: eeprom a ddress b it d efinitions b it ( s ) d efinition 15 parity bit - odd parity over entire address/data pair if there is a parity error, it will be re ported in bit-3 of th e regb register in the device configuration registers (offset 0x08e). 14 final address if 1, this will be the last data to be read. if 0, there will be more data to be read after this. 13:8 reserved - bits must be ?0? 7:0 target address - see table 3 table 3 shows the target addresses available for programmin g into bits 7:0 of the 16-bit address word. all other target addresses are reserved and must not be used. t able 3: t arget a ddress f or eeprom v alues t arget a ddress d ata e xar d efault 0x00 vendor id 0x13a8 0x01 device id 0x0358 - no slave 0x4358 - xr17v354 slave present 0x8358 - xr17v358 slave present 0x02 class code [7:0] lower 8-bits are reserved 0x0200 0x03 class code [23:8] 0x0700 0x04 subsystem vendor id 0x0000 0x05 subsystem id 0x0000 the second 16-bit word of the address/data pair is the data. the default values are shown in table 3 . the address/data pairs can be in any order. only the contents which need to be changed from the exar defaults need to be included in the eeprom. 0x104- 0x113 31:0 ro not implemented or not applicable (return zeros) 0x00000000 0x114 31:0 ro vc offset 0x4 0x8000000ff t able 1: pci l ocal b us c onfiguration s pace r egisters a ddress o ffset b its t ype d escription r eset v alue ( hex or binary )
xr17v358 15 rev. 1.0.4 high performance octal pci express uart 1.3 device internal register sets the device configuration registers and the eight individual uart configuration registers of the v358 occupy 8k of pci bus memory address space. these add resses are offset onto the basic memory address, a value loaded into the memory base address register (bar ) in the pci local bus configuration register set. the uart configuration registers are mapped into 8 addr ess blocks where each uart channel occupies 1024 bytes memory space for its own registers that incl ude the 16550 compatible registers. the device configuration registers are accessible from all uart chan nels. however, not all bits can be controlled by all channels. the uart channel can on ly control the 8xmode, 4xmode, reset and sleep regist er bits that apply to that particular channel. for example, this prevents channel 0 from accidentally resetting channel 1.
xr17v358 16 high performance octal pci express uart rev. 1.0.4 t able 4: xr17v358 uart and d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite c omment 0x0000 - 0x000f uart channel 0 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x0010 - 0x007f reserved 0x0080 - 0x009a device configuration registers ( table 5 ) 0x009b - 0x00ff reserved 0x0100 - 0x01ff uart 0 ? read fifo read-only 256 bytes of rx fifo data 0x0100 - 0x01ff uart 0 ? write fifo write-only 256 bytes of tx fifo data 0x0200 - 0x03ff uart 0 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x0400 - 0x040f uart channel 1 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x0410 - 0x047f reserved 0x0480 - 0x049a device configuration registers ( table 5 ) 0x049b - 0x04ff reserved 0x0500 - 0x05ff uart 1 ? read fifo read-only 256 bytes of rx fifo data 0x0500 - 0x05ff uart 1 ? write fifo write-only 256 bytes of tx fifo data 0x0600 - 0x07ff uart 1 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x0800 - 0x080f uart channel 2 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x0810 - 0x087f reserved 0x0880 - 0x089a device configuration registers ( table 5 ) 0x089b - 0x08ff reserved 0x0900 - 0x09ff uart 2 ? read fifo read-only 256 bytes of rx fifo data 0x0900 - 0x09ff uart 2 ? write fifo write-only 256 bytes of tx fifo data 0x0a00 - 0x0bff uart 2 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x0c00 - 0x0c0f uart channel 3 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x0c10 - 0x0c7f reserved 0x0c80 - 0x0c9a device configuration registers ( table 5 ) 0x0c9b - 0x0cff reserved 0x0d00 - 0x0dff uart 3 ? read fifo read-only 256 bytes of rx fifo data 0x0d00 - 0x0dff uart 3 ? write fifo write-only 256 bytes of tx fifo data 0x0e00 - 0x0fff uart 3 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr
xr17v358 17 rev. 1.0.4 high performance octal pci express uart 0x1000 - 0x100f uart channel 4 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x1010 - 0x107f reserved 0x1080 - 0x109a device configuration registers ( table 5 ) 0x109b - 0x10ff reserved 0x1100 - 0x11ff uart 4 ? read fifo read-only 256 bytes of rx fifo data 0x1100 - 0x11ff uart 4 ? write fifo write-only 256 bytes of tx fifo data 0x1200 - 0x13ff uart 4 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x1400 - 0x140f uart channel 5 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x1410 - 0x147f reserved 0x1480 - 0x149a device configuration registers ( table 5 ) 0x149b - 0x14ff reserved 0x1500 - 0x15ff uart 5 ? read fifo read-only 256 bytes of rx fifo data 0x1500 - 0x15ff uart 5 ? write fifo write-only 256 bytes of tx fifo data 0x1600 - 0x17ff uart 5 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x1800 - 0x180f uart channel 6 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x1810 - 0x187f reserved 0x1880 - 0x189a device configuration registers ( table 5 ) 0x189b - 0x18ff reserved 0x1900 - 0x19ff uart 6 ? read fifo read-only 256 bytes of rx fifo data 0x1900 - 0x19ff uart 6 ? write fifo write-only 256 bytes of tx fifo data 0x1a00 - 0x1bff uart 6 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x1c00 - 0x1c0f uart channel 7 regs ( table 13 & table 14 ) first 8 regs are 16550 compatible 0x1c10 - 0x1c7f reserved 0x1c80 - 0x1c9a device configuration registers ( table 5 ) 0x1c9b - 0x1cff reserved 0x1d00 - 0x1dff uart 7 ? read fifo read-only 256 bytes of rx fifo data 0x1d00 - 0x1dff uart 7 ? write fifo write-only 256 bytes of tx fifo data 0x1e00 - 0x1fff uart 7 ? read fifo with errors read-only 256 bytes of rx fifo data + lsr 0x2000 - 0x3fff uarts 8-15 via expansion port t able 4: xr17v358 uart and d evice c onfiguration r egisters o ffset a ddress m emory s pace r ead /w rite c omment
xr17v358 18 high performance octal pci express uart rev. 1.0.4 1.4 device configuration registers the device configuration registers provide easy progra mming of general operating parameters to the v358 and for monitoring the status of various functions. th ese registers control or report on all 8 channel uarts functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft -reset control, and device identification and revision, and others. tables 5 and 6 below show these registers in byte and dword alignment. each of these registers is described in detail in the following paragraphs. t able 5: d evice c onfiguration r egisters shown in byte alignment a ddress [a7:a0] r egister r ead /w rite c omment reset state ox080 int0 [7:0] read-only interrupt [7:0] bits [7:0] = 0x00 ox081 int1 [15:8] read-only bits [7:0] = 0x00 ox082 int2 [23:16] read-only bits [7:0] = 0x00 ox083 int3 [31:24] read-only bits [7:0] = 0x00 ox084 timercntl read/write timer control bits [7:0] = 0x00 ox085 rega reserved bits [7:0] = 0x00 ox086 timerlsb read/write timer lsb bits [7:0]= 0x00 ox087 timermsb read/write timer msb bits [7:0]= 0x00 individual uart channels can only control the bit pertaining to that channel in the registers at address offset 0x088-0x08b. ox088 8xmode read/write bits [7:0] = 0x00 ox089 4xmode read/write bits [7:0] = 0x00 ox08a reset write-only self clear bits after executing reset bits [7:0] = 0x00 ox08b sleep read/write sleep mode bits [7:0]= 0x00 ox08c drev read-only device revision bits [7:0] = current rev. ox08d dvid read-only device identification bits [7:0] = 0x88 ox08e regb read/write eeprom control bits [7:0] = 0x00 ox08f mpioint[7:0] read/write mpio[7:0] interrupt mask bits [7:0] = 0x00 ox090 mpiolvl[7:0] read/write mpio[7 :0] level control bits [7:0] = 0x00 ox091 mpio3t[7:0] read/write mpio[7:0] output control bits [7:0] = 0x00 ox092 mpioinv[7:0] read/write mpio[7:0] input polarity select bits [7:0] = 0x00 ox093 mpiosel[7:0] read/write mpio[7:0] select bits [7:0] = 0xff 0x094 mpiood[7:0] read/write mpio[7:0] open-drain output control bits [7:0] = 0x00 ox095 mpioint[15:8] read/write mpio[15: 8] interrupt mask bits [15:8] = 0x00 ox096 mpiolvl[15:8] read/write mpio[15:8] level control bits [15:8] = 0x00 ox097 mpio3t[15:8] read/write mpio[15:8] output control bits [15:8] = 0x00
xr17v358 19 rev. 1.0.4 high performance octal pci express uart 1.4.1 the global interrupt registers - int0, int1, int2 and int3 the xr17v358 has a 32-bit wide register [int0, int1, in t2 and int3] to provide interrupt information and supports two interrupt schemes. the first scheme is an 8-bit indicator representing all 8 channels with each bit representing each channel from 0 to 7. this permits t he interrupt service routine to quickly determine which uart channels need servicing so that it can go to t he appropriate uart channel interrupt service routines. int0 bit [0] represents the interrupt status for uart channel 0 when its transmitter, receiver, line status, or modem port status requires service. other bits in the int0 register provide indication for the other channels with bit [7] representing uart channel 7 respectively. the second scheme provides detail about the source of the interrupts for each uart channel. all the interrupts are encoded into a 3-bit code. this 3-bit code represen ts 7 interrupts corresponding to individual uart?s transmitter, receiver, line status, modem port status. int1 , int2 and int3 registers provide the 24-bit interrupt status for all 8 channels. bits [1 0:8] representing channel 0 and bits [31:29] representing channel 7 respectively. all 8 channel interrupts status are avail able with a single dword read operation. this feature allows the host another method to quickly service the interr upts, thus reducing the service interval and host bandwidth requirement. note that the interrupts reported in this register is specif ic to each uart channel. if there is a global interrupt such as the wake-up interrupt, timer/counter interrupt or mpio interrupt, they would be reported in the 3-bit code for channel 0 in int1. global interrupt register (dword) [default 0x00-00-00-00] int3 [31:24] int2 [23:16] int1 [15:8] int0 [7:0] all bits start up zero. a special interr upt condition is generated by the v358 upon awakening from sleep after all eight channels were put to sleep mode earlier. this wake -up interrupt is cleared by a read to the int0 register. figure 4 shows the 4-byte interrupt register and its make up. int0 [7:0] channel interrupt indicator ox098 mpioinv[15:8] read/write mpio[15:8] input polarity select bits [15:8] = 0x00 ox099 mpiosel[15:8] read/write mpio[15:8] select bits [15:8] = 0xff 0x09a mpiood[15:8] read/write mpio[15:8] open-drain output control bits [15:8] = 0x00 0x09b reserved 0x00 t able 6: d evice c onfiguration r egisters shown in dword alignment a ddress r egister b yte 3 [31:24] b yte 2 [23:16] b yte 1 [15:8] b yte 0 [7:0] 0x0080 - 0x0083 interrupt (read-only) int3 int2 int1 int0 0x0084-0x0087 timer (read/write) timermsb timerlsb reserved timercntl 0x0088-0x008b ancillary1 (read/write) sleep reset 4xmode 8xmode 0x008c-0x008f ancillary2 (read-only) mpioint[7:0] regb dvid drev 0x0090-0x0093 mpio1 (read/write) mpiosel[7:0] mpioinv[7:0] mpio3t[7:0] mpiolvl[7:0] 0x0094-0x0097 mpio2 (read/write) mpio3t[7:0] mpiolvl[15:8] mpioint[15:8] mpiood[7:0] 0x0098-0x009b mpio3 (read/write) reserved mpiood[15:8] mpiosel[15:8] mpioinv[15:8] t able 5: d evice c onfiguration r egisters shown in byte alignment a ddress [a7:a0] r egister r ead /w rite c omment reset state
xr17v358 20 high performance octal pci express uart rev. 1.0.4 each bit gives an indication of the channel that has requested for service. bit [0] represents channel 0 and bit [7] indicates channel 7. logic 1 indicates the channel n [7:0] has called for service. the interrupt bit clears after reading the appropriate register of the interr upting channel register, see interrupt clearing section. the int0 register provides individual status for each channel int0 register individual uart channel interrupt status ch-6 ch-7 ch-5 ch-4 ch-3 ch-2 ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 int3, int2 and int1 [31:8] 3-bit channel interrupt encoding each channel?s interrupt is encoded into 3 bits for receiv e, transmit, and status. bits [10:8] represent channel 0 and go up to channel 7 with bits [31:29]. the 3-bit encoding and their priority order are shown below in table 7 . the wake-up interrupt, timer/counter interrupt and mpio interrupt are only reported in channel 0 of int1 (bits[10:8]). these interrupts are not reported in any other location. f igure 4. t he g lobal i nterrupt r egister , int0, int1, int2 and int3 channel-3 channel-2 channel-1 channel-0 int2 register int1 register int3 register int0 register interrupt registers, int0, int1, int2 and int3 bit-0 bit-1 bit-2 bit-3 bit-7 bit-4 bit-5 bit-6 ch-3 ch-2 ch-1 ch-0 bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n bit n+1 bit n+2 bit n ch-7 ch-6 ch-5 ch-4 channel-7 channel-6 channel-5 channel-4 t able 7: uart c hannel [7:0] i nterrupt s ource e ncoding p riority b it [ n +2] b it [ n +1] b it [ n ] i nterrupt s ource ( s ) x 0 0 0 none or wake-up indicator (wake-up indicator is reported in channel 0 only) 1 0 0 1 rxrdy and rx line status (logic or of lsr[4:1]) 2 0 1 0 rxrdy time-out 3 0 1 1 txrdy, thr or tsr (auto rs485 mode) empty 4 1 0 0 msr, rts/cts or dtr/dsr delta or xoff /xon det. or special char. detected 5 1 0 1 reserved. 6 1 1 0 mpio pin(s). reported in channel 0 only. 7 1 1 1 timer/counter. reported in channel 0 only.
t able 8: uart c hannel [7:0] i nterrupt c learing wake-up indicator is cleared by reading the int0 register. rxrdy and rxrdy time-out is cleared by reading data in the rx fifo. rx line status interrupt clears after reading the lsr register that is in the uart channel register set. txrdy interrupt clears after reading isr register that is in the uart channel register set. modem status register interrupt clears after reading msr register that is in the uart channel register set. rts/cts or dtr/dsr delta interrupt clears after reading ms r register that is in the uart channel register set. xoff/xon delta and special character detect interrupt clears af ter reading the isr register that is in the uart channel reg - ister set. timer time-out interru pt clears after reading the timercntl register th at is in the device configuration register set. mpio interrupt clears after reading th e mpiolvl register that is in the device configuration register set. xr17v358 21 rev. 1.0.4 high performance octal pci express uart 1.4.2 general purpose 16-bit timer/counter [timermsb, ti melsb, timer, timecntl] ( default 0 x xx-xx-00-00) the xr17v358 has a general purpose 16-bit timer/coun ter. the internal 125mhz clock (master mode) or 62.5mhz clock (slave mode) or the external clock at th e tmrck input pin can be selected as the clock source for the timer/counter. the timer can be set to be a sing le-shot for a one-time event or re-triggerable for a periodic signal. an interrup t may be generat ed when the timer times out an d will show up as a channel 0 interrupt (see table 7 ). it is controlled through 4 configuration registers [t imercntl, timer, timelsb, timermsb]. the timercntl register provides the ti mer commands such as st art/stop, as shown in table 9 below. the time-out output of the timer can also be opti onally routed to the mpio[0] pin. the block diagram of the timer/counter circuit is shown below: f igure 5. t imer /c ounter circuit timer interrupt timer output mpiolvl[0] 0 1 0 1 timer interrupt no interrupt mpio[0] tmrck 125mhz/62.5mhz timercntl commands 16-bit timer/counter start/stop timer interrupt enable/ disable single shot/re-triggerable timermsb and timerlsb (16-bit value) 0 1 clock select route/de-route to mpio[0] timermsb [31:24] and timerlsb [23:16] registers the concatentaion of the 8-bit registers timermsb an d timerlsb forms a 16-bit value which decides the time-out period of the timer, per the following equation: timer output frequency = timer in put clock / 16-bit timer value the least-significant bit of the timer is being bit [0] of the timerlsb with most-significant-bit being bit [7] in timermsb. notice that these register s do not hold the current counter value when read. default value is zero (timer disabled) upon powerup and reset. the ?reset timer? command does not have any effect on this register.
timermsb register bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8 timerlsb register bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 16-bit timer/counter programmable registers xr17v358 22 high performance octal pci express uart rev. 1.0.4 rega [15:8] register reserved. timercntl [7:0] register the bits [3:0] of this register are used to issue comm ands. the commands are self-clearing, so reading this register does not show the last written command. reading this register returns a value of 0x01 when the timer interrupt is enabled and there is a pending timer interrup t. it returns a value of 0x00 at all other times. the default settings of the timer, upon power-up, a hardware reset or upon the issue of a ?timer reset? command are: timer interrupt disabled re-triggerable mode selected internal 125mhz clock (mas ter) or 62.5mhz clock (sla ve) selected as clock source timer output not routed to mpio[0] timer stopped t able 9: timer control r egisters timercntl [7:4] reserved timercntl [3:0] these bits are used to invoke a series of comm ands that control the func tion of the timer/counter. the commands 1100 to 1111 are reserved. 0001: enable timer interrupt 0010: disable timer interrupt 0011: select one-shot mode 0100: select re-triggerable mode 0101: select internal 125mhz clock (master) or 62.5mhz clock (slave) as clock input for the timer 0110: select external clock input through the tmrck pin for the timer 0111: route timer output to mpio[0] pin 1000: de-route timer output from mpio[0] 1001: start timer 1010: stop timer 1011: reset timer
xr17v358 23 rev. 1.0.4 high performance octal pci express uart timer operation the following paragraphs describ e the operation of the 16-bit timer/c ounter. the following conventions will be used in this discussion: ?n? is the 16-bit value programmed in the timer msb, lsb registers p +q = n, where ?p? and ?q? are approximately half of ?n?. if n is even, p = q = n/2. if n is odd, p = (n ? 1)/2 and q = (n + 1)/2. ?n? can take any value fr om 0x0002 to 0xffff. timer operation in one-shot mode: in the one-shot mode, the timer output will stay high wh en started (default state) and will continue to stay high until it times out (reac hes the terminal count of ?n? clocks), at which time it will become low and stay low. if the timer is re-started before the timer times out, the counter is reset and the timer will wait for another time-out period before setting its output low (see figure 6 ). if the timer times out, re-starting the timer does not have any effect and a ?stop timer? command needs to be issued first which will set the timer output to its default high state. the timer must be programmed while it is stopped since the following operations are blocked after the timer has been started: any write to timer msb, lsb registers issue of any command other than ?start timer?, ?stop timer? and ?reset timer? timer operation in re-triggerable mode: in the re-triggerabl e mode, when the timer is started, the timer outp ut will stay high until it reaches half of the terminal count n (= p clocks) and toggle low and stay low for a similar amount of time (q clocks). the above step will keep re peating until the timer is stopp ed at which time the output will become high (default state). see figure 6 . also, after the timer is started, re-starting the timer does not have any effect in re- triggerable mode. the timer must be programmed while it is stopped since the following operations are blocked when the timer is running: any write to timer msb, lsb registers issue of any command other than ?stop timer? and ?reset timer? (?start timer? is not allowed) routing the timer output to mpio[0] pin: mpio[0] pin is by default (on power up or reset, for ex ample) an input. however, whenever the timer output is routed to mpio[0] pin, mpio[0] will be automatically selected as an output mpio[0] will become high (the de fault state of timer output) all mpio control registers (mpiolvl , mpiosel etc) lose control over mpio[0] and get the control back only when the timer output is de-routed from mpio[0].
f igure 6. t imer o utput in o ne -s hot and r e - triggerable m odes timer output in re-triggerable mode timer output in one-shot mode after 'p' clocks start timer command issued start timer command issued 'n' clocks stop timer command issued start timer commands issued: less than 'n' clocks between successive commands < 'n' clocks after 'p' clocks after 'p' clocks after 'p' clocks after 'p' clocks after 'q' clocks after 'q' clocks after 'q' clocks after 'q' clocks < 'n' clocks xr17v358 24 high performance octal pci express uart rev. 1.0.4 timer interrupt in the one-shot mode, the timer will issue an interrupt upon timing out wh ich is ?n? clocks after the timer is started. in the re-triggerable mode , the timer will keep issuing an interrupt every ?n? clocks which is on every rising edge of the timer out put. the timer interrupt c an be cleared by reading the timercntl register or when a timer reset command is issued which brings the timer back to its default settings. the timercntl will read a value of 0x01 when the timer interrupt is enabled and there is a pending in terrupt. it reads a value of 0x00 at all other times. stopping the timer does no t clear the interrupt and neither does subsequent re- starting. f igure 7. i nterrupt o utput ( active low) in o ne -s hot and r e - triggerable m odes one-shot mode timer started timer timed out timercntl read re-triggerable mode timer timed out timercntl read timer timed out 1.4.3 8xmode [7:0] (default 0x00) each bit selects 8x or 16x sampling rate for that uart channel. the 8xmode register is accessible from the device configuration registers in all uart channels bu t the uart channel can only control the bit for that channel. for example, bit [0] is for channel 0 and can only be controlled by channel 0. all other bits are read- only in channel 0. logic 0 (default) selects normal 16x sampling (and 4xmode = 0x00) with logic one selects
xr17v358 25 rev. 1.0.4 high performance octal pci express uart 8x sampling rate. transmit and receiv e data rates will double by selectin g 8x. if using the 4xmode, the corresponding bit in this register should be logic 0 ch-6 ch-7 ch-5 ch-4 ch-3 ch-2 ch-1 ch-0 8xmode register individual uart channel 8x clock mode enabl e bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1.4.4 4xmode [15:8] (default 0x00) each bit selects 4x or 16x sampling rate for that uart channel. the 4xmode register is accessible from the device configuration registers in all uart channels bu t the uart channel can only control the bit for that channel. for example, bit [0] is channel 0 and can only be controlled by channel 0. all other bits are read-only in channel 0. logic 0 (default) selects normal 16x sa mpling (and 8xmode = 0x00) with logic one selects 4x sampling rate. transmit and receive data rates will quadruple by select ing 4x. if using the 8xmode, the corresponding bit in this register should be logic 0 ch-6 ch-7 ch-5 ch-4 ch-3 ch-2 ch-1 ch-0 4xmode register individual uart channel 4x clock mode enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 reset [23:16] (default 0x00) the 8-bit reset register prov ides the software with the ability to reset the uart(s) when there is a need. the reset register is accessib le from the device confi guration registers in all uart channels but the uart channel can only control the bit for that channel. fo r example, writing 0xff to t he reset register in channel 0 will only reset channel 0. each bit is se lf-clearing after it is wr itten a logic 1 to perform a reset to that channel. all registers in that channel will be re set to the default condition, see table 21 for details. . ch-6 ch-7 ch-5 ch-4 ch-3 ch-2 ch-1 ch-0 reset register individual uart channel reset enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1.4.5 sleep [31:24] (default 0x00) sleep register individual uart channel sleep enable ch-6 ch-7 ch-5 ch-4 ch-3 ch-2 ch-1 ch-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17v358 26 high performance octal pci express uart rev. 1.0.4 the 8-bit sleep register enables eac h uart separately to enter sl eep mode. the sleep register is accessible from the device configuration registers in all uart channels but the uart channel can only control the bit for that channel. for example, writing 0xff to the sleep re gister in channel 0 will only enable the sleep mode for channel 0. sleep mode reduces power consumption when the system needs to put the uart(s) to idle. the uart enters sleep mode when the following conditions are satisfied after the sleep mode is enabled (logic 0 (default) is to disable and logic 1 is to enable sleep mode): transmitter and receiver are empty (lsr[6]=1, lsr[0]=0) rx pin is idling at a high in normal mode or a low in infrared mode the modem inputs (cts#, dsr#, cd# and ri#) are st eady at either high or low (msr bits [3:0] = 0x0) the v358 is awakened by any of the following events occurring at any of the 8 uart channels: a receive data start bit transition (high to low in normal mode or from low to high in infrared mode) a data byte is loaded into the transmitter a change of logic state on any of the modem inputs so th at any of the delta bits (msr bits[3:0]) is set (ri# delta bit is only set on the rising edge) a receive data start bit transition will not wake up the uart if the multidrop mode is disabled (dld[6] = 0) and the receiver is disabled (msr[2] = 1, msr[0] = 0). a special interrupt is generat ed with an indication of no pending inte rrupt. the v358 will retu rn to sleep mode automatically after all interrupting condi tions have been serviced and cleared. it will stay in the sleep mode of operation until it is disabled by resetting the sleep register bits. 1.4.6 device identification and revision there are two internal registers that provide device iden tification and revision, dvid and drev registers. the 8-bit content in the dvid register provides device ident ification. a return value of 0x88 from this register indicates the device is a xr17v358. the drev register re turns an 8-bit value of 0x01 for revision a with 0x02 equals to revision b and so on. this information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. dvid [15:8] device identification for the type of uart . the device id of the xr17v358 is 0x88. drev [7:0] revision number of the xr17v358. a 0x01 represen ts "revision-a" with 0x02 for rev-b and so on. regb [23:16] (default 0x00) regb register provides a control for simultaneous write to all 8 uarts configuration register or individually. this is very useful for device initia lization in the power up and reset rout ines. also, the register provides a facility to interface to th e non-volatile memory devic e such as a 93c46 eeprom. in embedded applications, the user can use this facility to store propriet ary data in an external eeprom. 1.4.7 regb register regb[16](read/write) logic 0 (default) write to each uart configuration registers individually. logic 1 enables simultaneous write to all 8 uarts configuration register. regb[17](read/write) logic 0 (default) - wake-up interrupt is generated when uart exits sleep mode. logic 1 - no wake-up interrupt is generated when uart exits sleep mode.
xr17v358 27 rev. 1.0.4 high performance octal pci express uart 1.4.8 multi-purpose inputs and outputs the v358 provides 16 multi-purpose inputs/outputs mp io[15:0] for general use. each pin can be programmed to be an input or output function. the input logic state c an be set for normal or inverted level, and optionally set to generate an interrupt. the outputs can be set to be normal high or low state, 3-state, or open drain. their functions and definitions are programmed through 6 registers: mpioint, mpiolvl, mpio3t, mpioinv, mpiosel, and mpiood. if all 16 pins are set for inputs, all 16 interrupts would be ored together. the ored interrupt is reported in the channel 0 uart interrupt stat us, see interrupt status register. the pins may also be programmed to be outputs and to the 3-state condition fo r signal sharing. the mpio[0] pin can be programmed to show the timer output. when it is programmed to be the timer output, all the above 5 registers lose control over the mpio[0] pin. for details on timer output, please see ?section 1.4.2, genera l purpose 16-bit timer/ counter [timermsb, timelsb, timer, ti mecntl] (default 0xxx-xx-00-00)? on page 21 . 1.4.9 mpio registers regb[18](read/write logic 0 (default) - global interrupt enable. interrupts to pci host are enabled. logic 1 - global interrupt disable. interrupts to pci host are disabled. regb[19](read-only) logic 0 - eeprom load is valid. logic 1 - eeprom load error caused by one of the following co nditions: eeprom not attached, final bit not found, parity error detected. regb[20] (write-only) control the eeck, cl ock, output on the eeprom interface. regb[21] (write-only) control the eecs, chips select, output to the eeprom device. regb[22] (write-only) eedi data input. write data to the eeprom device. regb[23] (read-only) eedo data output. read data from the eeprom device. 1.4.7 regb register
xr17v358 28 high performance octal pci express uart rev. 1.0.4 there are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs. figure 8 shows the internal circuitry f igure 8. m ultipurpose i nput /o utput i nternal c ircuit mpio pin [15:0] mpiolvl [15:0] read input level mpioint [15:0] rising edge detection int and 1 0 mpiosel [15:0] (select input=1, output=0 ) mpio3t [15:0] (3-state enable =1) mpiolvl [15:0] (output level) mpioinv [15:0] (input inversion enable =1) mpiood [15:0] (open-drain enable =1) and and or .
xr17v358 29 rev. 1.0.4 high performance octal pci express uart mpioint [15:0] (default 0x00) the mpioint register enables the multipurpose input pin interrupt. if an mpio pin is selected by mpiosel as an input, then it can be selected to generate an interr upt. mpioint bit[0] enables input pin mpio0 for interrupt, and bit [7] enables input pin 7. no interrupt is enable if the pin is selected to be an output. the interrupt is edge sensing and determined by mpioinv and mpiolvl registers. the mpio interrupt clears after a read to register mpiolvl. the combination of mpiolvl and mpioinv determines the interrupt being active low or active high. logic 0 (default) disables th e pin?s interrupt and logic 1 enables it. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioint register multipurpose input/output interrupt enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpiolvl [15:0] (default 0x00) the mpiolvl register controls the outpu t pins and provides the input level st atus for the input pins. the status of the input pin(s) is read on this regi ster and output pins are controlled on this register. a logic 0 (default) sets the output to low and a logi c 1 sets the output pin to high. the mpio interrupt will clear upon reading this register. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiolvl register multipurpose output level control bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpio3t [15:0] (default 0x00) the mpio outputs can be tri-stated by the mpio3t regist er. a logic 0 (default) sets the output to active level per register mpiobit settling, a logic 1 sets the output pin to tri-state. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpio3t register multipurpose output 3-state enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpioinv [15:0] (default 0x00) the mpio inputs can be inverted by the mpioinv register. a logic 0 (default) does not invert the input pin logic. a logic 1 inverts the input logic level. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpioinv register multipurpose input signal inversion enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17v358 30 high performance octal pci express uart rev. 1.0.4 mpiosel [15:0](default 0xff) the mpiosel register defines the mpios as either an inpu t or output. a logic 1 (default) defines the pin for input and a logic 0 for output. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiosel registe r multipurpose input/output selection bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 mpiood [15:0] (default 0x00) the mpio outputs can behave as an open-drain output by the mpiood register. when the mpiood register is a logic 0 (default), the mpio is not an open-drain outp ut. a logic 1 enables the mpio as an open-drain output. this register has no effect, when the mpio is an input. mpio6 mpio7 mpio5 mpio4 mpio3 mpio2 mpio1 mpio0 mpiood register multipurpose open-drain output enable bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17v358 31 rev. 1.0.4 high performance octal pci express uart 2.0 transmit and receive data there are two methods to load transmit data and unload receive data from each uart channel. first, there is a transmit data register and receive data register for each uart channel as shown in table 4 set to ease programming. these registers support 8, 16 , 24 and 32 bits wide format. in the 32-bit format, it increases the data transfer rate on the pci bus. additionally, a special register location provides receive data byte with its associated error flags. this is a 16-bit or 32-bit read operation where the line status register (lsr) content in the uart channel register is paired along with the data byte. this operation fu rther facilitates data unloading with the error flags without having to read the lsr regi ster separately. furthermore, the xr17v358 supports 32-bit read/write operation. the second method is through each uart channel?s transmit holding register (thr) and receive holding register (rhr). the thr and rhr registers are 16550 comp atible so their access is limited to 8-bit format. the software driver must separately read the lsr cont ent for the associated error flags before reading the data byte. 2.1 fifo data loading and unloading in 32-bit format the xr17v358 supports 32-bit read and 32-bit write tr ansactions anywhere in the mapped memory region (except reserved areas). in a ddition, to utilize this feature fully, the device provides a separate memory location (apart from the individual channel?s r egister set) where the rx and the tx fifo can be read from/written to, as shown in table 4 . the following is an extract from the table s howing the memory locations that support 32-bit transactions: channel n: (for channels 0 through 7) where m = 4n + 1. rx fifo : 0xm00 - 0xmff (256 bytes) tx fifo : 0xm00 - 0xmff (256 bytes) rx fifo + status : 0x(m+1)0 - 0x(m+2)ff (256 bytes data + 256 bytes status) for example, the locations for channel 2 are: channel 2: rx fifo : 0x0900 - 0x09ff (256 bytes) tx fifo : 0x0900 - 0x09ff (256 bytes) rx fifo + status : 0x0a00 - 0x0bff (256 bytes data + 256 bytes status) 2.1.1 normal rx fifo data unloading at locations 0x100, 0x500, 0x900, 0xd00, 0x1100, 0x1500, 0x1900, and 0x1d00 the rx fifo data can be read out 32-bits at a time at memory locations 0x100 (channel 0), 0x500 (channel 1), 0x900 (channel 2),......., 0x 1d00 (channel 7). this operat ion is 4 times faster than reading the data in 256 separate 8-bit memory reads of rhr register (0x000 for channel 0, 0x400 for channel 1, 0x800 for channel 2,......, 0x1c00 for channel 7). r ead rx fifo, with n o e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 read n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc.
pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+3 receive data byte n+2 receive data byte n+1 receive data byte n+0 pci bus data bit-0 channel 0 to 7 receive data in 32-bit alignment through the configuration register address 0x0100, 0x0500, 0x0900, 0x0d00, 0x 1100, 0x1500, 0x1900 and 0x1d00 xr17v358 32 high performance octal pci express uart rev. 1.0.4 2.1.2 special rx fifo data unloading at locations 0x0200, 0x0600, 0x0a00, 0x0e00, 0x1200, 0x1600, 0x1a00, and 0x1e00 the xr17v358 also provides the same rx fifo data al ong with the lsr status information of each byte side- by-side, at locations 0x0200 (cha nnel 0), 0x0200 (channel 1), 0x0a00 (channel 2), ....., 0x1e00 (channel 7). the status and data bytes must be read in 16 or 32 bits format to maintain data in tegrity. the following tables show this clearly. r ead rx fifo, with lsr e rrors b yte 3 b yte 2 b yte 1 b yte 0 read n+0 to n+1 fifo data n+1 lsr n+1 fifo data n+0 lsr n+0 read n+2 to n+3 fifo data n+3 lsr n+3 fifo data n+2 lsr n+2 etc pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 receive data byte n+1 line status register n+1 receive data byte n+0 line status register n+0 pci bus data bit-0 channel 0 to 7 receive data with line status register in 32-bit alignment through the configuration register address 0x0200, 0x0600, 0x0a00, 0x0e00, 0x1200, 0x1600, 0x1a00 and 0x1e00 2.1.3 tx fifo data loading at locations 0x100, 0x500, 0x900, 0xd00, 0x1100, 0x1500, 0x1900, and 0x1d00 the tx fifo data can be loaded 32-bit (4 bytes) at a time at memory locations 0x0100 (channel 0), 0x0500 (channel 1), 0x0900 (channel 2), ............, 0x1900 (channel 6) a nd 0x1d00 (channel 7). w rite tx fifo b yte 3 b yte 2 b yte 1 b yte 0 write n+0 to n+3 fifo data n+3 fifo data n+2 fifo data n+1 fifo data n+0 write n+4 to n+7 fifo data n+7 fifo data n+6 fifo data n+5 fifo data n+4 etc.
pci bus data bit-31 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 transmit data byte n+3 transmit data byte n+2 transmit data byte n+1 transmit data byte n+0 pci bus data bit-0 channel 0 to 7 transmit data in 32-bit alignment through the configuration register address 0x0100, 0x0500, 0x0900, 0x0d00, 0x1100, 0x1500, 0x1900 and 0x1d00 xr17v358 33 rev. 1.0.4 high performance octal pci express uart 2.2 fifo data loading and unloading through the uart channel registers, thr and rhr in 8-bit format the thr and rhr register address for channel 0 to channel 7 is shown in table 10 below. the thr and rhr for each channel 0 to 7 are located sequentially at address 0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0a000, 0x0c00 and 0x0e00. transmit data byte is loaded to the thr when writing to that address and receive data is unloaded from the rhr register when reading that address. both thr and rhr registers are 16c550 compatible in 8-bit format, so each bus operation can only write or read in bytes. t able 10: t ransmit and r eceive d ata r egister in b yte format , 16c550 compatible thr and rhr address locations for ch0 to ch7 (16c550 compatible) ch0 0x0000 write thr ch0 0x0000 read rhr ch1 0x0400 write thr ch1 0x0400 read rhr ch2 0x0800 write thr ch2 0x0800 read rhr ch3 0x0c00 write thr ch3 0x0c00 read rhr ch4 0x1000 write thr ch4 0x1000 read rhr ch5 0x1400 write thr ch5 0x1400 read rhr ch6 0x1800 write thr ch6 0x1800 read rhr ch7 0x1c00 write thr ch7 0x1c00 read rhr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
xr17v358 34 high performance octal pci express uart rev. 1.0.4 3.0 uart there are 8 uarts channel [7:0] in the v358. each has its own 256-byte of transmit and receive fifo, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. eight additional registers per uart were added for the exar enhanced features. 3.1 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit [7] sets the prescaler to divide the internal 125mhz clock (master) or 62.5mhz clock (slave) by 1 or 4. the output of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 and (2 16 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16x, 8x or 4x sampling clock of the serial data rate. the sampling clock is used by the transmi tter for data bit shifting and receiver for data sampling. the brg divisor (dll, dlm and dld registers) defaults to 1 (dll = 0x01, dlm = 0x00, dld = 0x00). the dll and dlm registers provide the integer part of the divisor and the dld re gister provides the fractional part of the divisor. only the four lower bits of the dld are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111) . programming the baud rate generator registers dll, dlm and dld provides the capability fo r selecting the operating data rate. table 11 shows the divisor for some standard and non-standard data rates when using the internal 125mhz clock at 16x clock rate. table 12 shows the divisor for some standard and non-standard data rates when using the internal 62.5mhz clock at 16x clock rate. if the pre-scaler is used (mcr bit [7] = 1), the output data rate will be 4 times less than that shown in table 11 and table 12 . at 8x sampling rate, these data rates would double. at 4x sampling rate, these data rates would quadruple. also , when using 8x or 4x sampling mode, note that the bit-time will have a jitter (+/- 1/16) whenever the dld is an odd number. for data rates not listed in table 11 , the divisor value can be calculated with the following equation(s): required divisor (decimal) = (125mhz or 62.5mhz clo ck frequency / prescaler) / (serial data rate x 16), with 8xmode =0 and 4xmode = 0 required divisor (decimal) = (125mhz or 62.5mhz clock frequency / prescaler / (serial data rate x 8), with 8xmode = 1 and 4xmode = 0 required divisor (decimal) = (125mhz or 62.5mhz clock frequency / prescaler / (serial data rate x 4), with 8xmode = 0 and 4xmode = 1 round( (required divisor - trunc (required divisor) )*16)/16 + trunc (required divisor), where dlm = trunc( required divisor) >> 8 dll = trunc (required divisor) & 0xff dld = round ( (required divisor- trunc(required divisor) )*16) the closest divisor that is obtainable in the v3 58 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10.
f igure 9. b aud r ate g enerator 125 mhz clock (master) or 62.5 mhz clock (slave) mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x, 8x or 4x sampling rate clock to transmitter and receiver to other channels fractional baud rate generator logic xr17v358 35 rev. 1.0.4 high performance octal pci express uart
t able 11: t ypical data rates with i nternal 125mh z clock at 16x s ampling (m aster m ode ) r equired o utput d ata r ate d ivisor for 16x clock (decimal) d ivisor o btainable in v358 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex)) d ata e rror r ate (%) 2400 3255.21 3255 3/16 0c b7 3 0 4800 1627.60 1627 9/16 06 5b 9 0 9600 813.80 813 12/16 03 2d c 0.01 10000 781.25 781 4/16 03 0d 4 0 19200 406.90 406 14/16 01 96 e 0.01 25000 312.5 312 8/16 01 38 8 0 28800 271.27 271 4/16 01 0f 4 0.01 38400 203.45 203 7/16 00 cb 7 0.01 50000 156.25 156 4/16 00 9c 4 0 57600 135.63 135 10/16 00 87 a 0.01 75000 104.17 104 2/16 00 68 2 0.04 100000 78.125 78 2/16 00 4e 2 0 115200 67.82 67 13/16 00 43 d 0.01 153600 50.86 50 13/16 00 32 d 0.10 200000 39.06 39 1/16 00 27 1 0 225000 34.72 34 11/16 00 22 b 0.10 230400 33.91 33 14/16 00 21 e 0.10 250000 31.25 31 4/16 00 1f 4 0 300000 26.04 26 00 1a 0 0.16 400000 19.53 19 8/16 00 13 8 0.16 460800 16.95 16 15/16 00 10 f 0.10 500000 15.625 15 10/16 00 0f a 0 576000 13.56 13 9/16 00 0d 9 0.01 750000 10.42 10 6/16 00 0a 6 0.40 921600 8.48 8 7/16 00 08 7 0.47 1000000 7.81 7 13/16 00 07 d 0 1152000 6.78 6 12/16 00 06 c 0.47 xr17v358 36 high performance octal pci express uart rev. 1.0.4
t able 12: t ypical data rates with 62.5mh z clock at 16x s ampling (s lave m ode ) r equired o utput d ata r ate d ivisor for 16x clock (decimal) d ivisor o btainable in v358 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex)) d ata e rror r ate (%) 2400 1627.60 1627 9/16 06 5b 9 0 4800 813.80 813 12/16 03 2d c 0 9600 406.90 406 14/16 01 96 e 0.01 10000 390.63 390 10/16 01 86 a 0 19200 203.45 203 7/16 00 cb 7 0.01 25000 156.25 156 4/16 00 9c 4 0 28800 135.63 135 10/16 00 87 a 0.01 38400 101.73 101 11/16 00 65 b 0.04 50000 78.13 78 2/16 00 4e 2 0 57600 67.82 67 13/16 00 43 d 0.01 75000 52.08 52 1/16 00 34 1 0.04 100000 39.06 39 1/16 00 27 1 0 115200 33.91 33 14/16 00 21 d 0.10 153600 25.43 25 6/16 00 19 6 0.22 200000 19.53 19 8/16 00 13 8 0.16 225000 17.36 17 5/16 00 11 5 0.28 230400 16.95 16 15/16 00 10 f 0.10 250000 15.63 15 10/16 00 0f a 0 300000 13.02 13 0/16 00 0d 0 0.16 400000 9.77 9 12/16 00 09 c 0.16 460800 8.48 8 7/16 00 08 7 0.47 500000 7.81 7 13/16 00 07 d 0 576000 6.78 6 12/16 00 06 c 0.47 750000 5.21 5 3/16 00 05 3 0.40 921600 4.24 4 3/16 00 04 3 1.22 1000000 3.91 3 14/16 00 03 e 0.81 1152000 3.39 3 6/16 00 03 6 0.47 xr17v358 37 rev. 1.0.4 high performance octal pci express uart
xr17v358 38 high performance octal pci express uart rev. 1.0.4 3.2 automatic hardware (rts/cts or dtr/dsr) flow control operation automatic hardware or rts/dtr and cts/dsr flow control is used to prevent data overrun to the local receiver fifo and remote receiver fifo. the rts#/dtr # output pin is used to request remote unit to suspend/restart data transmission while the cts#/dsr # input pin is monitored to suspend/restart local transmitter. the auto rts/dtr and auto cts/dsr flow cont rol features are individually selected to fit specific application requirement and enabled through efr bit[7 :6] and mcr bit [2] for either rts/cts or dtr/dsr control signals. the auto rts/dtr function must be star ted by asserting rts/dtr# output pin (mcr bit [0] or bit [1] to logic 1) after it is enabled. figure 10 below explains how it works. two interrupts associated with rts/dtr and cts/dsr flow control have been added to give indication when rts/dtr# pin or cts/dsr# pin is de-asserted during operation. the rts/dtr and cts/dsr interrupts must be first enabled by efr bit [4], and then enabled indivi dually by ier bits [7:6], an d chosen with mcr bit [2]. automatic hardware flow contro l is selected by setting bits [7 (cts): 6 (rts)] of the efr register to logic 1. if cts# pin transitions from low to high indicating a flow control request, isr bit [5] will be set to logic 1, (if enabled via ier bit [7:6]), and the uart will suspend tx tr ansmissions as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input returns to low, indicating more data may be sent.
f igure 10. a uto rts/dtr and cts/dsr f low c ontrol o peration rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1 the local uart (uarta) starts data transf er by asserting -rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. xr17v358 39 rev. 1.0.4 high performance octal pci express uart
xr17v358 40 high performance octal pci express uart rev. 1.0.4 3.3 infrared mode each uart in the v358 includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.1. the input pin enir conveniently activates all 8 uart channels to start up in the infrared mode. this global control pin enables the mcr bit [6] function in every uart channel register. after power up or a reset, the software can overwrite mcr bit [6 ] if so desired. enir and mcr bit [6] also disable its receiver while the transmitter is sending data. this prev ents the echoed data from going to the receiver. the global activation enir pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. when the infrared feature is enabled, the tr ansmit data outputs, tx[7:0], would idle low. likewise, the rx [7:0] inputs assume a low idle level. the infrared encoder sends out a 3/16 of a bit wide pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 11 below. typical max data rate for the infrared encoder with a 3/16 of a bit wide pulse is 115.2 kbps. for data rates above 115.2 kbps and up to1.152 mbps, fast ir mode can be enabled via dld bit-4 for a 1/4 of bit wide pulse. for exact 3/16 or 1/4 of a bit wide pul se, the 16x sampling rate should be used and dld[3:0] = ?0000?. the ir pulse width can va ry if dld[3:0] is not ?0000?. the infrared decoder receives the input pulse from th e infrared sensing diode on rx pin. each time the decoder senses a light pulse, it returns a "0" to the data bit stream. the rx input signal may be inverted prior delivered to the input of the decoder vi a internal register setting. this op tion supports active low instead of normal active high pulse from so me infrared modules on the market. f igure 11. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 or 1/4 bit time irencoder-1 character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder- 1 r x data r eceive i r pulse ( rx pin)
xr17v358 41 rev. 1.0.4 high performance octal pci express uart 3.4 internal loopback each uart channel provides an inte rnal loopback capabilit y for system di agnostic. the in ternal loopback mode is enabled by setting mcr register bit [4] to a lo gic 1. all regular uart functions operate normally. figure 12 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held at high or mark co ndition while rts# and dtr# are de-asserted. the cts#, dsr#, cd# and ri# inputs are ignored. f igure 12. i nternal l oop b ack tx [7:0] r x [7:0] modem / general purpose control logic internal bus lines and control signals r ts# [7:0 ] mcr bit-4=1 vcc vcc vcc transmit shift register r eceive shift register c ts# [7:0 ] d tr # [7:0 ] d sr # [7:0 ] r i# [7:0] cd# [7:0] op1# op2# rts# cts# dtr# dsr# ri# cd#
xr17v358 42 high performance octal pci express uart rev. 1.0.4 3.5 uart channel configuration registers address lines a0 to a3 select the 16 registers in each channel. the first 8 registers are 16550 compatible with exar enhanced feature registers lo cated on the upp er 8 addresses. t able 13: uart channel configuration registers a ddress r egister r ead /w rite c omments a3 a2 a1 a0 16550 c ompatible 0 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1 0 0 0 1 dlm - divisor msb read/write lcr[7] = 1 0 0 1 0 dld - divisor fractional read/write lcr[7] = 1 0 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only lcr[7] = 0 0 0 1 1 lcr - line control register read/write 0 1 0 0 mcr - modem control register read/write 0 1 0 1 lsr - line status register read-only 0 1 1 0 msr - modem status register - auto rs485 delay read-only write-only efr bit-4 = 1 0 1 1 1 spr - scratch pad register read/write e nhanced r egister 1 0 0 0 fctr - feature control register read/write 1 0 0 1 efr - enhanced function register read/write 1 0 1 0 txcnt - transmit fifo level counter txtrg - transmit fifo trigger level read-only write-only 1 0 1 1 rxcnt - receive fifo level counter rxtrg - receive fifo trigger level read-only write-only 1 1 0 0 xoff-1 - xoff character 1 xchar write-only read-only xon,xoff rcvd. flags 1 1 0 1 xoff-2 - xoff character 2 write-only 1 1 1 0 xon-1 - xon character 1 write-only 1 1 1 1 xon-2 - xon character 2 write-only
xr17v358 43 rev. 1.0.4 high performance octal pci express uart t able 14: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it [7] b it [6] b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] c omment 0 0 0 0 rhr r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=0 0 0 0 0 thr w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=0 0 0 0 0 dll r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 0 1 dlm r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 1 0 dld r/w invert rs485 polarity multi- drop mode xon/ xoff parity check fast ir mode bit [3] bit [2] bit [1] bit [0] lcr[7]=1 0 0 0 1 ier r/w 0/ 0/ 0/ 0 modem status int. enable rx line status int. enable tx empty int. enable rx data int. enable lcr[7]=0 cts/ dsr# int. enable rts/ dtr# int. enable xon/ xoff/sp. char. int. enable 0 0 1 0 isr r fifos enable fifos enable 0/ 0/ int source bit [3] int source bit [2] int source bit [1] int source bit [0] lcr[7]=0 delta - flow cntl xoff/spe - cial char 0 0 1 0 fcr w r x f i f o trigger r x f i f o trigger 0/ 0/ dma mode tx fifo reset rx fifo reset fifos enable lcr[7]=0 tx fifo trigger tx fifo trigger 0 0 1 1 lcr r/w divisor enable set tx break set par - ity even par - ity parity enable stop bits word length bit [1] word length bit [0] 0 1 0 0 mcr r/w 0/ 0/ 0/ internal loopback enable (op2) 1 (op1) 1 rts# pin con - trol dtr# pin con - trol brg pres - caler ir enable xonany tx char immedi - ate rts/ dtr flow sel 0 1 0 1 lsr r rx fifo error tsr empty thr empty rx break rx framing error rx par - ity error rx overrun rx data ready 0 1 1 0 msr r cd ri dsr cts delta cd# delta ri# delta dsr# delta cts# msr w rs485 dly[3] rs485 dly[2] rs485 dly[1] rs485 dly[0] disable tx disable rx disable tx mode disable rx mode 0 1 1 1 spr r/w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] user data 1 0 0 0 fctr r/w trg ta b l e bit [1] trg ta b l e bit [0] auto rs485 enable invert ir rx input rts/ dtr hyst bit [3] rts/ dtr hyst bit [2] rts/ dtr hyst bit [1] rts/ dtr hyst bit [0]
xr17v358 44 high performance octal pci express uart rev. 1.0.4 n ote : mcr bits [3:2] (op1 and op2 outputs) are not avai lable in the xr17v358. they are present for 16c550 compatibility during internal loopback, see figure 12 . 3.6 transmitter the transmitter section comprises of a 256 bytes of fifo, a byte-wide transmit holding register (thr) and an 8-bit transmit shift register (tsr). thr receives a data byte from the host (non-fifo mode) or a data byte from the fifo when the fifo is enabled by fcr bit [0]. tsr shifts out every data bit with the 16x or 8x internal clock. a bit time is 16 or 8 clock periods. th e transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). the st atus of the thr and tsr are reported in the line status register (lsr bit [6:5]). 3.6.1 transmit holdin g register (thr) the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-sign ificant-bit (bit [0]) becomes first data bit to go out. the thr is also the input register to the transmit fifo of 256 bytes when fifo operation is enabled by fcr bit[0]. a thr empty interrupt can be generated when it is enabled in ier bit [1]. 3.6.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit [5]) is set when the data byte is transferred to tsr. thr flag can generate a transmit empty interrupt (i sr bit [1]) when it is enabled by ier bit [1]. the tsr flag (lsr bit [6 ]) is set when tsr beco mes completely empty. 1 0 0 1 efr r/w auto cts/ dsr enable auto rts/ dtr enable special char select enable ier [7:5], isr [5:4], fcr[5:4], mcr[7:5], msr soft - ware flow cntl bit [3] soft - ware flow cntl bit [2] soft - ware flow cntl bit [1] software flow cntl bit [0] 1 0 1 0 txcnt r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 0 txtrg w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 1 rxcnt r bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 0 1 1 rxtrg w bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 1 1 0 0 xchar r 0 0 0 0 tx xon indicator tx xoff indicator xon det. indicator xoff det. indicator self clear after read 1 1 0 0 xoff1 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 0 1 xoff2 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 1 0 xon1 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] 1 1 1 1 xon2 w bit [7] bit [6] bit [5] bit [4] bit [3] bit-2 bit [1] bit [0] t able 14: uart channel configurati on registers description. s haded bits are enabled by efr b it -4. a ddress a3-a0 r eg n ame r ead / w rite b it [7] b it [6] b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] c omment
f igure 13. t ransmitter o peration in non -fifo m ode transmit holding register (thr) transm it shift register (tsr) data byte l s b m s b t h r in te rru p t (is r b it-1 ) enabled by ier bit-1 16x or 8x or 4x clock xr17v358 45 rev. 1.0.4 high performance octal pci express uart 3.6.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 256 bytes of transmit data. the thr empt y flag (lsr bit [5]) is set whenever the fifo is empty. th e thr empty flag can generate a transm it empty interrupt (isr bit [1]) when the amount of data in the fifo falls below it s programmed trigger level (see txtrg register). the transmit empty interrupt is enabled by ier bit [1]. the tsr flag (lsr bit [6]) is set when tsr becomes completely empty. furthermore, with the rs485 half-d uplex direction control enabled (fctr bit [5]=1) the source of the transmit empty interrupt changes to tsr empty instead of thr empty. this is to ensure the rts# output is not changed until the last st op bit of the last character is shifted out. 3.6.4 auto rs485 operation the auto rs485 half-duplex direction control changes the behavior of the transmitter when enabled by fctr bit [5]. it de-asserts rts# or dtr# after a specified delay indicate d in msr[7:4] following the last stop bit of the last character that has been transmitted. this helps in turning around the transceiver to receive the remote station?s response. the delay optimizes the time needed fo r the last transmission to reach the farthest station on a long cable network before switching off the line driver. this delay prevents undesirable line signal disturbance that causes signal degradation. it also changes the transmitter empt y interrupt to tsr empty instead of thr empty. f igure 14. t ransmitter o peration in fifo and f low c ontrol m ode transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below programmed trigger level (txtrg) and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo (256-byte) 16x or 8x or 4x clock auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.
xr17v358 46 high performance octal pci express uart rev. 1.0.4 3.7 receiver the receiver section contains an 8-bit receive shift r egister (rsr) and receive holding register (rhr). the rsr uses the 16x, 8x or 4x clock for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an inter nal receiver counter starts counting at the 16x, 8x or 4x clock rate. after 8 or 4 or 2 clocks the start bit period should be at the center of the start bit. at this time the start bit is sampled and if it is still a logic 0 it is validated. evaluati ng the start bit in this manner prevents the receiver from assembling a false ch aracter. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if there were any error(s), they are reported in the lsr register bits [4:1]. upon unloading th e receive data byte from rhr, the receive fifo pointer is bumped and the error flags are immediately up dated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay until it reaches the fifo trigger level. furthermore, data delivery to th e host is guaranteed by a re ceive data ready time-out function when receive data does not reach the receive fifo trigger level. this time-out delay is 4 word lengths as defined by lcr bits [1:0] plus 12 bits ti me. the rhr interrupt is enabled by ier bit [0]. 3.7.1 receiver operation in non-fifo mode f igure 15. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) 16x or 8x or 4x clock receive data characters data bit validation error flags in lsr bits 4:2
xr17v358 47 rev. 1.0.4 high performance octal pci express uart 3.7.2 receiver operation with fifo f igure 16. r eceiver o peration in fifo and f low c ontrol m ode receive data shift register (rsr) 16x or 8x or 4x clock error flags (256-sets) error flags in lsr bits 4:2 256 bytes by 11-bits wide fifo receive data characters fifo trigger=128 example: - fifo trigger level set at 128 bytes - rts/dtr hyasteresis set at +/-32 chars. data fills to 160 data falls to 96 data bit validation receive data fifo (256-byte) receive data receive data byte and errors rhr interrupt (isr bit-2) is programmed at fifo trigger level (rxtrg). fifo is enable by fcr bit-0=1 rts#/dtr# de-asserts when data fills above the trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-2. rts#/dtr# re-asserts when data falls below the trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-2. 3.7.3 normal multidrop (9-bit) mode normal multidrop mode is enabled when dld[6] = 1 and ef r[5] = 0 (special characte r detect disabled). the receiver is set to force pari ty 0 (lcr[5:3] = ?111?) in or der to detect address bytes. with the receiver initially di sabled (msr[2] = 1), it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). this address byte will cause the uart to set the parity error. the uart will generate an lsr interrupt and place the address byte in the rx fifo. the software then examines the byte and enables the receiver if the address matches its slave address, otherwise, it does not enable the receiver. if the receiver has been enabled, the receiver will receiv e the subsequent data. if an address byte is received, it will generate an lsr inte rrupt. the software again examines the byte and if the addr ess matches its slave address, it does not have to do any thing. if the address does not match its slave address, then the receiver should be disabled. 3.7.4 auto address detection mode auto address detection mode is enabled when dld[6] = 1 and efr bit-5 = 1 (special character detect enabled). the receiver is set to force parity 0 (lcr[5:3] = ?111?) in order to detect address bytes. the desired slave address will need to be written into the xoff2 register. the re ceiver will monitor all incoming address bytes and compare with the programmed character in the xoff2 register. if the received byte is a data byte or an address byte that does not match th e programmed character in the xoff2 register, the receiver will discard the data. upon receiving an addre ss byte that matches the xoff2 charac ter, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the rx fifo along with the parity bit (in place of the parity error bit). th e receiver also generates an lsr inte rrupt. the receiver will then receive the subsequent data. if another address byte is rece ived and this address does not match the programmed xoff2 character, then the re ceiver will automatically be disabled and a ll subsequent data is ignored until there is another address byte match with xoff2.
xr17v358 48 high performance octal pci express uart rev. 1.0.4 4.0 uart configuration registers 4.1 receive holding register (rhr) - read only see?receiver? on page 46. 4.2 transmit holding register (thr) - write only see?transmitter? on page 44. 4.3 baud rate generator divisors (dlm, dll and dld) dlm[7:0], dll[7:0] and dld[3:0] the baud rate generator (brg) generates the data rate for the transmitter and receiver. the rate is programmed through registers dlm, dll and dld which are on ly accessible when lcr bit [7] is set to logic 1. refer to ?section 3.1, programmable baud rate ge nerator with fractional divisor? on page 34 for more details. dld[7]: rs-485 polarity x logic 0 = the auto rs-485 half-duplex direction control pin will be high for tx and low for rx. x logic 1 = the auto rs-485 half-duplex direction control pin will be low for tx and high for rx. dld[6]: multi-drop mode x logic 0 = normal mode. x logic 1 = enable multi-drop mode. dld[5]: xon/xoff parity check x logic 0 = xon/xoff characters are valid flow contro l characters even if they have parity errors. x logic 1 = xon/xoff characters are not valid flow control characters if they have parity errors. dld[4]: fast ir mode x logic 0 = if ir mode is enabled, ir pulsewidth will be 3/16th of bit time. x logic 1 = if ir mode is enabled, ir pulsewidth will be 1/4th of bit time. 4.4 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are reported in the interrupt status register (isr) and also encoded in int (int0-int3) register in the device configuration registers. 4.4.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit [0] = logic 1) and receive interrupts (ier bit [0] = logic 1) are enabled, the rhr interrupts (see isr bits [4:3 ]) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit [0]) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty.
xr17v358 49 rev. 1.0.4 high performance octal pci express uart 4.4.2 ier versus receive/transmit fifo polled mode operation when fcr bit [0] equals a logic 1 for fifo enable; resett ing ier bits [3:0] enables the xr16v358 in the fifo polled mode of operation. since the receiver and transmitte r have separate bits in the lsr either can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr (non-fifo mode) or rx fifo (fifo mode). b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr (non-fifo mode) or tx fifo (fifo mode) is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[7]: cts# input interrupt enable (requires efr bit [4]=1) x logic 0 = disable the cts# interrupt (default). x logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high. ier[6]: rts# output interrupt enable (requires efr bit [4]=1) x logic 0 = disable the rts# interrupt (default). x logic 1 = enable the rts# interrupt. the uart issues an interrupt when rts# pin makes a transition from low to high. ier[5]: xoff interrupt enable (requires efr bit [4]=1) x logic 0 = disable the software flow cont rol, receive xoff interrupt (default). x logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details. ier[4]: reserved ier[3]: modem status interrupt enable the modem status register interrupt is issued whenever any of the delta bits of the msr register (bits [3:0]) is set. x logic 0 = disable the modem status register interrupt (default). x logic 1 = enable the modem status register interrupt. ier[2]: receive line status interrupt enable an overrun error, framing error, pari ty error or detection of a break character will result in an lsr interrupt. the v358 will issue an lsr interrupt imm ediately after receiving a character wit h an error. it will again re-issue the interrupt (if the first one has been cleared by reading the lsr register) when the character with the error is on the top of the fifo, meaning the next one to be read out of the fifo. for example, let?s consider an incoming data stream of 0x55, 0xaa, etc. and t hat the character 0xaa has a parity error associated with it. let?s assume that the c haracter 0x55 has not been read out of the fi fo yet. the v358v358 will issue an interrup t as soon as the stop bit of the charac ter 0xaa is received. the lsr register will have only the fifo error bit (bit [7]) set and none of the other error bits (bits [4:1]) will be se t, since the byte on the top of the fifo is 0x55 which does not have any erro rs associated with it. when this byte has been read out, the v358 will issue another lsr interrupt and this time the lsr re gister will show the pari ty bit (bit [2]) set. x logic 0 = disable the receiver line status interrupt (default). x logic 1 = enable the receiver line status interrupt.
xr17v358 50 high performance octal pci express uart rev. 1.0.4 ier[1]: tx ready interrupt enable in non-fifo mode, a tx interrupt is issued whenever the thr is empty. in the fifo mode, an interrupt is issued twice: once when the number of bytes in the tx fifo falls below the programmed trigger level and again when the tx fifo becomes empty. when autors485 mode is enabled (fctr bit [5] = 1), the second interrupt is delayed until the transmitter (both t he tx fifo and the tx shift register) is empty. x logic 0= disable transmit ready interrupt (default). x logic 1 = enable transmit ready interrupt. ier[0]: rx interrupt enable the receive data ready in terrupt will be issued when rhr has a data character in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. x logic 0 = disable the receive data ready interrupt (default). x logic 1 = enable the receiver data ready interrupt. 4.5 interrupt status register (isr) - read only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current highe st pending interrupt level to be serviced, others queue up for next service. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source ta b l e , table 15 , shows the data values (bit [5:0]) for the six pr ioritized interrupt levels and the interr upt sources associated with each of these interrupt levels. 4.5.1 interrupt generation: x lsr is by any of the lsr bits [4:1]. see ier bit [2] description on the previous page. x rxrdy is by rx trigger level. x rxrdy time-out is by a 4-char plus 12 bits delay timer. x txrdy is by tx trigger level or tx fifo empty (or transmitter empty in auto rs-485 control). x msr is by any of the msr bits [3:0]. x receive xoff/xon/special character is by detection of a xoff, xon or special character. x cts#/dsr# is when its transmitter toggles the input pin (from low to high) during auto cts/dsr flow control enabled by efr bit [7] and selection on mcr bit [2]. x rts#/dtr# is when its receiver toggles the output pin (from low to high) during auto rts/dtr flow control enabled by efr bit [6] and selection on mcr bit [2]. x wake-up indicator is when the uart wakes up from the sleep mode. 4.5.2 interrupt clearing: x lsr interrupt is cleared by a read to the lsr register. x rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. x rxrdy time-out interrupt is cleared by reading rhr. x txrdy interrupt is cleared by a read to the isr register or writing to thr. x msr interrupt is cleared by a read to the msr register. x xoff/xon interrupt is cleared by reading isr. x special character interrupt is cleared by a read to isr. x rts#/dtr# and cts#/dsr# status change interrupts are cleared by a read to the msr register.
xr17v358 51 rev. 1.0.4 high performance octal pci express uart ? wake-up indicator is cleared by a read to the int0 register. ] t able 15: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of the interrupt l evel b it [5] b it [4] b it [3] b it [2] b it [1] b it [0] 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 0 1 0 0 rxrdy (received data ready) 3 0 0 1 1 0 0 rxrdy (receive data time-out) 4 0 0 0 0 1 0 txrdy (transmitter holding register empty) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xon/xoff or special character) 7 1 0 0 0 0 0 cts#/dsr#, rts#/dtr# change of state x 0 0 0 0 0 1 none (default) isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. isr[5:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority levels (see table 15 ). see ?section 4.5.1, interrupt generation:? on page 50 and ?section 4.5.2, interrupt clearing:? on page 50 for details. isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending. (default condition) 4.6 fifo control register (fcr) - write only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) the fctr bits [5:4] are associated with these 2 bits. these 2 bits are used to set the trigger level for the receive fifo. the uart will issue a rece ive interrupt when the nu mber of the characters in the fifo crosses the trigger level. table 16 shows the complete selections. note that the receiver and the transmitter cannot use different trigger tables. whichever selection is made last applies to both the rx and tx side. fcr[5:4]: transmit fifo trigger select (requires efr bit [4]=1) (logic 0 = default, tx trigger level = 1) the fctr bits [7:6] are associated with these 2 bits by selecting one of the four tables. the 4 user selectable trigger levels in 4 tables are sup ported for compatibility reasons. these 2 bits set the trigger level for the transmit fifo interrup t. the uart will issue a transmit interrupt when the number of char acters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 16 below shows the selections.
xr17v358 52 high performance octal pci express uart rev. 1.0.4 fcr[3]: dma mode select this bit has no effect since txrdy and rxrdy pins are no t available in this device. it is provided for legacy software compatibility. x logic 0 = set dma to mode 0 (default). x logic 1 = set dma to mode 1. fcr[2]: tx fifo reset this bit is only active when fcr bit [0] is active. x logic 0= no transmit fifo reset (default). x logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[1]: rx fifo reset this bit is only active when fcr bit [0] is active. x logic 0 = no receive fifo reset (default). x logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[0]: tx and rx fifo enable x logic 0 = disable the transmit and receive fifo (default). x logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. t able 16: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able fctr bit [7] fctr bit [6] fcr bit [7] fcr bit [6] fcr bit [5] fcr bit [4] r eceive t rigger l evel t ransmit t rigger l evel c ompatibility ta b l e - a 0 0 0 0 1 1 0 1 0 1 0 0 1 (default) 4 8 14 1 (default) 16c550, 16c2550, 16c2552, 16c554, 16c580, 16l580 ta b l e - b 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 28 16 8 24 30 16c650a, 16l651
xr17v358 53 rev. 1.0.4 high performance octal pci express uart 4.7 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[7]: baud rate divisors enable baud rate generator divisor (dll, dlm, dld) enable. x logic 0 = data registers are selected (default). x logic 1 = divisor latch registers (dll, dlm and dld) are selected. lcr[6]: transmit break enable when enabled the break control bit causes a break condition to be transmitted (the tx output is forced to a ?space", low, state). this condition remains unt il disabled by setting lcr bit [6] to a logic 0. x logic 0 = no tx break condition. (default) x logic 1 = forces the transmitter output (tx) to a ?space?, low, for alerting the remote receiver of a line break condition. lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit [5] selects the forc ed parity format. x lcr bit [5] = logic 0, parity is not forced (default). x lcr bit [5] = logic 1 and lcr bit [4] = logic 0, parity bi t is forced to a logical 1for the transmit and receive data. x lcr bit [5] = logic 1 and lcr bit [4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. table-c 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 56 60 8 16 32 56 16c654 table-d 1 1 x x x x programmable via rxtrg register programmable via txtrg register 16l2752, 16l2750, 16c2852, 16c850, 16c854, 16c864 t able 16: t ransmit and r eceive fifo t rigger t able and l evel s election t rigger t able fctr bit [7] fctr bit [6] fcr bit [7] fcr bit [6] fcr bit [5] fcr bit [4] r eceive t rigger l evel t ransmit t rigger l evel c ompatibility
t able 17: p arity p rogramming bit [5] bit [4] bit [3] p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, ?1? 1 1 1 forced parity to space, ?0? xr17v358 54 high performance octal pci express uart rev. 1.0.4 lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bi t [3] set to a logic 1, lcr bit [4] se lects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gene rated by forcing an even th e number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 17 above for parity selection summary. ? logic 0 = no parity. ? logic 1 = a parity bit is generated during the transmissi on while the receiver checks for parity error of the data character received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 4.8 modem control regist er (mcr) - read/write the mcr register is used for controlling the modem interface signals or gener al purpose inputs/outputs. lcr lcr lcr bit [2] bit [1] bit [0]
xr17v358 55 rev. 1.0.4 high performance octal pci express uart mcr[7]: clock prescaler select (requires efr bit [4]=1) x logic 0 = divide by one. the internal 125mhz clock (mast er) or 62.5mhz clock (slave) is fed directly to the programmable baud rate generator without furthe r modification, i.e., di vide by one (default). x logic 1 = divide by four. the prescaler divides the inte rnal 125mhz clock (master) or 62.5mhz clock (slave) by 4 and feeds it to the programmable baud rate generator, hence, data rates become one forth. mcr[6]: infrared encoder/decoder enable (requires efr bit [4]=1) the state of this bit depends on the sampled logic level of pin enir during power up, following a hardware reset (rising edge of rst# input). afterward user can override this bit for desired operation. x logic 0 = enable the standard modem receive and transmit character interface. x logic 1 = enable infrared irda receive and transmit inputs/outputs. while in this mode, the tx/rx output/ input are routed to the in frared encoder/ decoder. the data input and output levels will confor m to the irda infrared interface requiremen t. as such, while in this mode the infr ared tx output will be a low during idle data conditions. fctr bit [4] may be selected to inve rt the rx input signal level going to the decoder for infrared modules that provide rather an inverted output. for exact 3/16 or 1/4 bit wide pulse, the 16x sampling rate must be used and dld[3:0] = ?0000?. if dld[3:0] is not ?0000? , the pulse width can vary. mcr[5]: xon-any enable (requires efr bit [4]=1) x logic 0 = disable xon-any function (default). x logic 1 = enable xon-any function. in this mode any rx character re ceived will enable xon, resume data transmission. mcr[4]: internal loopback enable x logic 1 = disable loopback mode (default). x logic 1 = enable local loopback mode, see loopback section and figure 12 . mcr[3]: send char immediate (op2 in local loopback mode) this bit is used to transmit a character immediately irrespective of the bytes currently in the transmit fifo. the data byte must be loaded into the transmit holding regi ster (thr) immediately followin g the write to this bit (to set it to a ?1?). in other words, no other register must be accessed between setting this bit and writing to the thr. the loaded byte will be transmitted ahead of all t he bytes in the tx fifo, immediately after the character currently being shifted out of the transmit shift register is sent out. the existing lin e parameters (parity, stop bits) will be used when compos ing the character. this bit is self cleari ng, therefore, must be set before sending a custom character each time. please note that the transm itter must be enabled for th is function (msr[3] = 0). also, if software flow control is enabled, the software fl ow control characters (xon, xoff) have higher priority and will get shifted out before the custom by te is transmitted. x logic 0 = send char immediate disabled (default). x logic 1 = send char immediate enabled. in local loopback mode (mcr[4] = 1), this bit acts as the legacy op2 output and controls the cd bit in the msr register as shown in figure 12 . please make sure that this bit is a ?0? when exiting the local loopback mode.
xr17v358 56 high performance octal pci express uart rev. 1.0.4 mcr[2]: dtr# or rts# for auto flow control (op1 in local loopback mode) dtr# or rts# auto hardware flow control select. this bi t is in effect only when auto rts/dtr is enabled by efr bit [6]. dtr# selection is associat ed with dsr# and rts# is with cts#. x logic 0 = uses rts# and cts# pins for auto hardware flow control. x logic 1 = uses dtr# and dsr# pins for auto hardware flow control. in local loopback mode (mcr[4] = 1), this bit acts as t he legacy op1 output and cont rols the ri bit in the msr register, as shown in figure 12 . mcr[1]: rts# output the rts# pin may be used for automatic hardware flow co ntrol by enabled by efr bit [6] and mcr bit [2]=0. if the modem interface is not used, this output may be used for general purpose. x logic 0 = force rts# output to a high (default). x logic 1= force rts# output to low. mcr[0]: dtr# output the dtr# pin may be used for automatic hardware flow control enabled by efr bit [6] and mcr bit [2]=1. if the modem interface is not used, this output may be used for general purpose. x logic 0 = force dtr# output to a high (default). x logic 1 = force dtr# output to a low. 4.9 line status register (lsr) - read only this register provides the status of data transfers between the uart and the host. if ier bit [2] is set to a logic 1, an lsr interrupt will be generated immediately when any characte r in the rx fifo has an error (parity, framing, overrun, break). lsr[7]: receive fifo data error flag x logic 0 = no fifo error (default). x logic 1 = an indicator for the sum of all error bits in th e rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit cl ears when there are no more errors in the fifo. lsr[6]: transmitter empty flag this bit is the transmitter em pty indicator. this bit is set to a logic 1 whenever both the tr ansmit fifo (or thr, in non-fifo mode) and the transmit shift register (tsr) ar e both empty. it is set to logic 0 whenever either the tx fifo or tsr contains a data character. lsr[5]: transmit fifo empty flag this bit is the transmit fifo empty indicator. this bit indicates that the transmitter is ready to accept a new character for transmission. this bit is set to a logic high when the last data byte is transferred from the transmit fifo to the transmit shift register. the bit is reset to logic 0 as soon as a data byte is loaded into the transmit fifo. in the non-fifo mode th is bit is set when the transmit hold ing register (thr) is empty; it is cleared when at a byte is written to the thr. lsr[4]: receive break flag x logic 0 = no break condition (default). x logic 1 = the receiver received a break signal (rx was low for one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle cond ition, ?mark? or high.
xr17v358 57 rev. 1.0.4 high performance octal pci express uart lsr[3]: receive data framing error flag x logic 0 = no framing error (default). x logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[2]: receive data parity error flag x logic 0 = no parity error (default). x logic 1 = parity error. the receive character in rhr (top of the fifo) does not have correct parity information and is suspect. this error is associat ed with the character ava ilable for reading in rhr. lsr[1]: receiver overrun flag x logic 0 = no overrun error (default). x logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[0]: receive data ready indicator x logic 0 = no data in receive holding register or fifo (default). x logic 1 = data has been received and is save d in the receive holding register or fifo. 4.10 modem status register (msr) - read only this register provides the current state of the modem interface signals, or othe r peripheral device that the uart is connected. lower four bits of this register are used to indicate the changed information. these bits are set to a logic 1 whenever a signal from the modem changes state. these bits may be used as general purpose inputs/outputs when they are not used with modem signals. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit [3] in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loopback mode this bit is equivalent to bit [2] in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status dsr# pin may function as automatic hardware flow contro l signal input if it is enabled and selected by auto cts/dsr bit (efr bit [6]=1) and rts/dtr flow control select bit (mcr bit [2]=1). auto cts/dsr flow control allows starting and stopping of local data transmis sions based on the modem dsr# signal. a high on the dsr# pin will stop uart transmitter as soon as the curren t character has finished transmission, and a low will resume data transmission . normally msr bit [5] is the complement of the dsr# input. however in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts/dsr bit (efr bit [6]=1) and rts/dtr flow control select bit (mcr bit [2]=0). auto cts/dsr flow control allows starting and stopping of lo cal data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitter as soon as the cu rrent character has finished transmission, and a low will resume data transmission. normally msr bit [4] is the co mplement of the cts# input. however in the loopback mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used.
xr17v358 58 high performance octal pci express uart rev. 1.0.4 msr[3]: delta cd# input flag x logic 0 = no change on cd# input (default). x logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if ms r interrupt is enabled (ier bit [3]). msr[2]: delta ri# input flag x logic 0 = no change on ri# input (default). x logic 1 = the ri# input has changed from a low to a high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit [3]). msr[1]: delta ds r# input flag x logic 0 = no change on dsr# input (default). x logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit [3]). msr[0]: delta cts# input flag x logic 0 = no change on cts# input (default). x logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit [3]). 4.11 modem status register (msr) - write only the upper four bits [7:4] of this register set the delay in number of bits time for the auto rs-485 turn around from transmit to receive. msr [7:4]: auto rs485 turn-around delay (requires efr bit [4]=1) when auto rs485 feature is enabled (fctr bit [5]=1) and rts#/dtr# output is connected to the enable input of a rs-485 transceiver. these 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. this dela y controls when to change the state of rts#/dtr# output. this delay is very useful in long-cable networks. table 18 shows the selection. the bits are enabled by efr bit-4.
t able 18: a uto rs485 h alf - duplex d irection c ontrol d elay from t ransmit - to -r eceive d elay in d ata b it ( s ) t ime 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 9 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 xr17v358 59 rev. 1.0.4 high performance octal pci express uart msr [3]: transmitter disable this bit can be used to disable the transmitter by halting the transmit shift register (tsr). when this bit is set to a logic 1, the bytes already in the fifo will not be sent out. also, any more data loaded into the fifo will stay in the fifo and will not be sent ou t. when this bit is set to a logic 0, the bytes currently in the tx fifo will be sent out. please note that setting this bit to a logic 1 stops any character from going out. also, this bit must be a logic 0 for the send char immediate function (see mcr[3]). ? logic 0 = enable transmitter (default). ? logic 1 = disable transmitter. msr[7] msr[6] msr[5] msr[4]
xr17v358 60 high performance octal pci express uart rev. 1.0.4 msr [2]: receiver disable this bit can be used to disable the receiver by halting th e receive shift register (rsr). when this bit is set to a logic 1, the receiver will oper ate in one of the following ways: if a character is being received at the time of sett ing this bit, that character will be correctly received. no more characters will be received. if the receiver is idle at the time of setting this bit, no more characters will be received. the receiver can be enabled an d will start receiving characters by resettin g this bit to a logi c 0. the receiver will operate in one of the following ways: if the receiver is idle (rx pin is hi gh) at the time of setting this bit, the next characte r will be received normally. it is recommended that the receiver be idle when resetting this bit to a logic 0. if the receiver is not idle (rx pin is toggling) at the time of setting this bit, the rx fifo will be filled with unknown data. any data that is in the rx fifo can be read out at any time whether the re ceiver is disabled or not. x logic 0 = enable receiver (default). x logic 1 = disable receiver. msr [1]: transmitter disable modes this bit is only applicable when msr[3] = 1. x logic 0 = no xon/xoff software flow control characters will be transmitted when the tran smitter is disabled. if there is a pending xon/xoff character to be sent while the transmitter is di sabled, it will be transmitted. no additional xon/xoff characters will be sent. x logic 1 = xon/xoff software flow control characters will be transmitte d even though the transmitter is disabled. msr[0]: receiver disable modes this is only applicable when msr[2] = 1. x logic 0 = all rx data and xon/xoff flow control characters are ignored. x logic 1 = all rx data is ignored. xon/xoff fl ow control characters are detected and acted upon. 4.12 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the co ntent of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle. 4.13 feature control register (fctr) - read/write this register controls the uart enhanced functions that are not available on st16c554 or st16c654. fctr[7:6]: tx and rx fifo trigger table select these 2 bits select the transmit and receive fifo trigger level table a, b, c or d. when table a, b, or c is selected the auto rts flow c ontrol trigger level is set to "next fifo trigger level" for compatibility to st16c550 and st16c650 series. rts/dtr# triggers on the next leve l of the rx fifo trigger level, in another word, one fifo level above and one fi fo level below. see in table 16 for complete selection with fcr bit [5:4] and fctr bits [7:6], i.e. if table c is used on the receiv er with rx fifo trigger level set to 56 bytes, rts/dtr# output will de-assert at 60 and re-assert at 16.
xr17v358 61 rev. 1.0.4 high performance octal pci express uart fctr[5]: auto rs485 enable auto rs485 half duplex control enable/disable. rts# or dtr# can be selected as the control output via mcr bit-2. note that this feature ha s precedence over the auto rts/dtr flow control feature (efr bit-6). therefore, the auto rts/dt r flow control feature will not have any effect when the auto rs485 half-duplex direction control feature is enabled. ? logic 0 = standard st16c550 mode. transmitter generates an interrupt when transmit holding register (thr) becomes empty. transmit shift regist er (tsr) may still be shifting data bit out. ? logic 1 = enable auto rs485 half duplex direction cont rol. rts#/dtr# output changes from high to low when finished sending the last stop bit of the last character out of the tsr register. it changes from low to high when a data byte is loaded in to the thr or transmit fifo. the change to high occurs prior sending the start-bit. it also changes the transmitter interrupt from transmit holding to tr ansmit shift register (tsr) empty. if software flow control is enabled, the rts# /dtr# output will not change if the tx fifo is empty and the rx fifo level generates an xon or xoff character to be transmitted. fctr[4]: infrared rx input logic select ? logic 0 = select rx input as active high encoded irda data, normal, (default). ? logic 1 = select rx input as active low encoded irda data, inverted. fctr [3:0] - auto rts/dtr fl ow control hysteresis select these bits select the auto rts/dtr flow control hyster esis and only valid when tx and rx trigger table-d is selected (fctr bit [7:6] are set to logic 1). the rts/dtr hysteresis is referenced to the rx fifo trigger level. after reset, these bits are set to logic 0 selecting the next fifo trigger level for hardware flow control. table 19 below shows the 16 selectab le hysteresis levels. t able 19: 16 s electable h ysteresis l evels w hen t rigger t able -d is s elected fctr b it [3] fctr b it [2] fctr b it [1] fctr b it [0] rts/dtr h ysteresis ( characters ) 0 0 0 0 0 0 0 0 1 +/- 4 0 0 1 0 +/- 6 0 0 1 1 +/- 8 0 1 0 0 +/- 8 0 1 0 1 +/- 16 0 1 1 0 +/- 24 0 1 1 1 +/- 32 1 1 0 0 +/- 12 1 1 0 1 +/- 20 1 1 1 0 +/- 28 1 1 1 1 +/- 36 1 0 0 0 +/- 40 1 0 0 1 +/- 44 1 0 1 0 +/- 48 1 0 1 1 +/- 52
xr17v358 62 high performance octal pci express uart rev. 1.0.4 4.14 enhanced feature register (efr) - read/write enhanced features are enabled or disabled using this register. bits [3:0] provide single or dual consecutive character software flow control selection (see table 20 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[7]: auto cts flow control enable automatic cts or dsr flow control. x logic 0 = automatic cts/dsr flow control is disabled (default). x logic 1 = enable automatic cts/dsr flow control. transmission stops when cts/dsr# pin de-asserts (high). transmission resumes when ct s/dsr# pin is asserted (low). th e selection for cts# or dsr# is through mcr bit [2]. efr[6]: auto rts or dtr flow control enable rts#/dtr# output may be used for hardware flow control by setting efr bit [6] to logic 1. when auto rts/ dtr is selected, an in terrupt will be gener ated when the receive fifo is f illed to the progra mmed trigger level and rts/dtr# will de-assert (high) at the next upper trigger or selected hysteresis level. rts/dtr# will re- assert (low) when fifo data falls be low the next lower trigger or selected hysteresis level (see fctr bits 4- 7). the rts# or dtr# output must be asserted (low) before the auto rts/dtr can take effect. the selection for rts# or dtr# is through mcr bit [2]. rts/dtr# pin will function as a general purpose output when hardware flow control is disabled. x logic 0 = automatic rts/dtr flow control is disabled (default). x logic 1 = enable automatic rts/dtr flow control. efr[5]: special character detect enable x logic 0 = special character detect disabled (default). x logic 1 = special character detect enabled. the ua rt compares each incoming receive character with data in xoff-2 register. if a match ex ists, the received data will be transferred to fifo and isr bit [4] will be set to indicate detection of the special character. bit [0] corresponds with the lsb bit for the receive character. if flow control is set for comparing xon1, xoff1 (efr [1:0]=10) then flow control and special character work normally . however, if flow control is set for comp aring xon2, xoff2 (efr[1:0]=01) then flow control works normally, but xoff2 will not go to the fifo, and will gen erate an xoff interrupt and a special character interrupt. efr[4]: enhanced function bits enable enhanced function control bit. this bit enables the enhan ced functions in ier bits [7:5], isr bits [5:4], fcr bits [5:4], mcr bits [7:5] and msr [7:0] bits to be mo dified. after modifying any enhanced bits, efr bit [4] can be set to a logic 0 to latch the new values. this feature prevents legacy software from altering or overwriting the enhanced functions once set. normally, it is recommended to leave it enabled. x logic 0 = disable write access to the enhanced function bits: ier bits [7:5], isr bits [5:4], fcr bits [5:4], mcr bits [7:5] and msr [7:0] bits. after a reset, all these bits are set to a logic 0 to be compatible with st16c550 mode (default). x logic 1 = enables write access to the enhanced function bits: ier bits [7:5], isr bits [5:4], fcr bits [5:4], mcr bits [7:5] and msr [7:0] bits.
xr17v358 63 rev. 1.0.4 high performance octal pci express uart efr[3:0]: software flow control select combinations of software flow control can be selected by programming these bits, as shown in table 20 . t able 20: s oftware f low c ontrol f unctions t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2 receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control receiver compares xon1 and xon2, xoff1 and xoff2 software flow control can not be used when the auto rs-485 half-duplex direction control feature is enabled (fctr[5]=1). with this feature enabled, the rts#/dtr# output controls the direction of the half-duplex rs- 485 transceiver. the rts#/dtr# output changes the dire ction of the half-duplex transceiver to the transmit mode when data is being tr ansmitted from the uart on the tx outpu t. however, the rts#/dtr# output will remain in the receive direction if th e tx fifo is empty and the rx fifo triggers an xon or xoff character to be transmitted. 4.15 txcnt[7:0]: transmit fifo level counter - read only transmit fifo level byte count from 0x00 (0 bytes) to 0xff (255 or 256 bytes). this 8-bit register gives an indication of the number of characters in the transmit fifo. the fifo level byte count register is read only. the user can take advantage of the fi fo level byte counter for faster data loading to the transmit fifo, which reduces cpu bandwidth requirements. 4.16 txtrg [7:0]: transmit fi fo trigger level - write only an 8-bit value written to this register sets the tx fifo trigger level from 0x00 (zero) to 0xff (255). the tx fifo trigger level generates an interrupt whenever the data level in the transmit fifo falls below this preset trigger level. 4.17 rxcnt[7:0]: receive fifo level counter - read only receive fifo level byte count from 0x00 (0 bytes) to 0xff (255 or 256 bytes). it gives an indication of the number of characters in the receive fifo. the fifo leve l byte count register is read only. the user can take advantage of the fifo level byte counter for faster data unloading from the receiver fifo, which reduces cpu bandwidth requirements. efr bit [3] efr bit [2] efr bit [1] efr bit [0]
xr17v358 64 high performance octal pci express uart rev. 1.0.4 4.18 rxtrg[7:0]: receive fifo trigger level - write only an 8-bit value written to this register, sets the rx fi fo trigger level from 0x00 (zero) to 0xff (255). the rx fifo trigger level generates an interrupt whenever the receive fifo level rises to this preset trigger level. 4.19 xoff1, xoff2, xon1 and xon2 registers - write only these registers are used to program the xoff1, xoff 2, xon1 and xon2 control characters respectively. 4.20 xchar register - read only this register gives the status of the last sent contro l character (xon or xoff) and the last received control character (xon or xoff). this register will be reset to 0x00 if, at anytime, the softwa re flow control is disabled. xchar [7:4]: reserved xchar [3]: transmit xon indicator if the last transmitted contro l character was a xon characte r or characters (xon1, xon2) , this bit will be set to a logic 1. this bit will clear after the read. xchar [2]: transmit xoff indicator if the last transmitted control character was a xoff character or characters (x off1, xoff2), this bit will be set to a logic 1. this bit will clear after the read. xchar [1]: xon detect indicator if the last received control character was a xon charac ter, xon characters (xon1, xon2) or an xon-any character, this bit will be set to a lo gic 1. this bit will clear after the read. xchar [0]: xoff detect indicator if the last received co ntrol character was a xo ff character or characters (xoff1 , xoff2), this bit will be set to a logic 1. this bit will clear after the read.
t able 21: uart reset conditions dll bits [7:0] = 0x01 tx[7:0] high dlm bits [7:0] = 0x00 irtx[7:0] low dld bits [7:0] = 0x00 rts#[7:0] high rhr bits [7:0] = 0xxx dtr#[7:0] high thr bits [7:0] = 0xxx eeck low ier bits [7:0] = 0x00 eecs low fcr bits [7:0] = 0x00 eedi low isr bits [7:0] = 0x01 lcr bits [7:0] = 0x00 mcr bits [7:0] = 0x00 lsr bits [7:0] = 0x60 msr bits [3:0] = logic 0 bits [7:4] = logic levels of the inputs spr bits [7:0] = 0xff fctr bits [7:0] = 0x00 efr bits [7:0] = 0x00 txcnt bits [7:0] = 0x00 txtrg bits [7:0] = 0x00 rxcnt bits [7:0] = 0x00 rxtrg bits [7:0] = 0x00 xchar bits [7:0] = 0x00 xon1 bits [7:0] = 0x00 xon2 bits [7:0] = 0x00 xoff1 bits [7:0] = 0x00 xoff2 bits [7:0] = 0x00 xr17v358 65 rev. 1.0.4 high performance octal pci express uart registers reset state i/o signals reset state
absolute maximum ratings power supply range 3.6 volts voltage at any pin -0.5 to vcc+0.5v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw thermal resistance (176-fpbga) theta-ja = 31.6 o c/w, theta-jc = 15.2 o c/w electrical characteristics dc electrical characteristics o to o c ( industrial grade ) s upply v oltage , vcc33 = 3.3v10% s ymbol p arameter m in m ax u nit s c ondition n otes v il input low voltage -0.3 0.6 v v ih input high voltage 2.4 vcc33 v v ol output low voltage 0.4 v i ol = 6 ma v oh output high voltage 2.4 v i oh = -4ma i cc power supply current 100 ma total for all vcc33 power supplies xr17v358 66 high performance octal pci express uart rev. 1.0.4 ta=-40 +85
package dimensions (176-fpbga) b a e d c a1 corner f h g j k m n p l 1 32 4 5 7 8 9 10 6 d1 12 13 14 d1 d 11 d e b a1 a a2 (a1 corner feature is mfger option) plane seating r 1515 xr17v358 67 rev. 1.0.4 high performance octal pci express uart n ote : a 0.047 0.059 1.20 1.50 a1 0.010 0.014 0.25 0.35 a2 0.037 0.045 0.95 1.15 d 0.508 0.516 12.90 13.10 d1 0.441 bsc 11.20 bsc b 0.018 0.022 0.45 0.55 e 0.031 bsc 0.80 bsc note: the control dimension is the millimeter column inches millimeters symbol min max min max
68 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2012 exar corporation datasheet april 2012. send your uart technical inquiry with technical details to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr17v358 high performance octal pci express uart rev. 1.0.4 revision history d ate r evision d escription april 2009 p1.0.0 preliminary datasheet. april 2009 p1.0.1 fixed typo in pin descriptions. g12 should be "vcc12" as shown in figure 2 and not "vcc33". july 2009 p1.0.2 added preliminary dc electrical characteristics. clarified vcc33 and vcc12 pin descriptions. december 2009 rev 1.0.0 final datasheet. updated dc electrical specs. september 2010 rev 1.0.1 corrected pin "trst#" polarity. december 2010 rev 1.0.2 corrected device status on page 2 to "active". april 2011 rev 1.0.3 removed the "msi-x capable capability id" on page 12 table 1. april 2012 rev 1.0.4 removed the references to "burst mode" (fast back to back transactions) in section 2 since this feature is not sup ported in the pcie specs (only in the pci specs). therefore, it is not supported by the xr17v358.

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